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PDF ( 数据手册 , 数据表 ) K60P100M100SF2

零件编号 K60P100M100SF2
描述 Up to 100 MHz ARM Cortex-M4 core
制造商 Freescale Semiconductor
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K60P100M100SF2 数据手册, 描述, 功能
Freescale Semiconductor
Data Sheet: Product Preview
Document Number: K60P100M100SF2
Rev. 4, 3/2011
K60 Sub-Family Data Sheet
Supports the following:
MK60N256VLL100, MK60X256VLL100,
MK60N512VLL100
Features
Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Memories and memory interfaces
– Up to 512 KB program flash memory on non-
FlexMemory devices
– Up to 256 KB program flash memory on
FlexMemory devices
– Up to 256 KB FlexNVM on FlexMemory devices
– 4 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
System peripherals
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 64
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
www.DataSheet4U.com
K60P100M100SF2
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– Hardware random-number generator
– Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
– 128-bit unique identification (ID) number per chip
Human-machine interface
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
Analog modules
– Two 16-bit SAR ADCs
– Programmable gain amplifier (up to x64) integrated
into each ADC
– 12-bit DAC
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
Timers
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel quadrature decoder/general purpose
timers
– IEEE 1588 timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
This document contains information on a product under development. Freescale
reserves the right to change or discontinue this product without notice.
© 2010–2011 Freescale Semiconductor, Inc.
Preliminary







K60P100M100SF2 pdf, 数据表
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Max.
1.2
Unit
V
3.5 Result of exceeding a rating
40
30
20 The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
10
0
Measured characteristic
Operating rating
www.DataSheet4U.com
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
8
Preliminary
Freescale Semiconductor, Inc.







K60P100M100SF2 equivalent, schematic
General
Table 6. Power consumption operating behaviors (continued)
Symbol
IDD_RUN
Description
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
IDD_RUN_M
AX
Run mode current — all peripheral clocks
enabled and peripherals active, code executing
from flash
• @ 1.8V
• @ 3.0V
Min.
Typ.
40
42
55
56
85
85
Max.
TBD
TBD
TBD
TBD
TBD
TBD
Unit
mA
mA
mA
mA
mA
mA
Notes
2
3
4
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
IDD_STOP Stop mode current at 3.0 V
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
IDD_VLPW Very-low-power wait mode current at 3.0 V
IDD_VLPS Very-low-power stop mode current at 3.0 V
IDD_LLS Low leakage stop mode current at 3.0 V
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• 128KB RAM devices
• 64KB RAM devices
35
15
0.4
1.25
TBD
1.05
50
12
8
6
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
2
5
6
7
8
IDD_VLLS2
IDD_VLLS1
IDD_VBAT
Very low-leakage stop mode 2 current at 3.0 V
Very low-leakage stop mode 1 current at 3.0 V
Average current when CPU is not accessing
RTC registers at 3.0 V
4
TBD
μA
2
TBD
μA
550 TBD nA
9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
www.DataeSahcehetm4oUd.cuolem's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, but peripherals are not in active operation.
4. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, and peripherals are in active operation.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
16
Preliminary
Freescale Semiconductor, Inc.










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