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PDF ( 数据手册 , 数据表 ) K524G2GACB-A050

零件编号 K524G2GACB-A050
描述 4Gb NAND Flash + 2Gb Mobile DDR
制造商 Samsung semiconductor
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K524G2GACB-A050 数据手册, 描述, 功能
K524G2GACB-A050
MCP MEMORY
MCP Specification
4Gb NAND Flash + 2Gb Mobile DDR
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
www.DataSheeatp4pUli.ccaotmions where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 - Revision 1.3
November 2009







K524G2GACB-A050 pdf, 数据表
K524G2GACB-A050
7. FUNCTIONAL BLOCK DIAGRAM
VCCn
VSSn
/CEn
/REn
/WPn
/WEn
ALEn
CLEn
R/Bn
4Gb NAND
Flash Memory
MCP MEMORY
IO0n to IO15n
CKd,/CKd
CKEd
/CSd
/RASd
/CASd
/WEd
A0d ~ A13d
BA0d ~ BA1d
DM0d ~ DM3d
DQS0d ~ DQS3d
VDDd VDDQd VSSd VSSQd
2Gb Mobile DDR
DQ0d~DQ31d
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- 8 - Revision 1.3
November 2009







K524G2GACB-A050 equivalent, schematic
K524G2GACB-A050
MCP MEMORY
1.8 Read / Program / Erase Characteristics
Parameter
Program Time
Number of Partial Program Cycles
Block Erase Time
Symbol
Min
Typ
Max
Unit
tPROG
-
250 750
µs
Nop - - 4 cycles
tBERS
-
2 10 ms
NOTE :
1) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V Vcc and 25°C temperature.
1.9 AC Timing Characteristics for Command / Address / Data Input
Parameter
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
Address to Data Loading Time
Symbol
tCLS(1)
tCLH
tCS(1)
tCH
tWP
tALS(1)
tALH
tDS(1)
tDH
tWC
tWH
tADL(2)
Min
21
5
21
5
21
21
5
20
5
40
10
100
NOTE :
1) The transition of the corresponding control pins must occur only once while WE is held low
2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle
Max
-
-
-
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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- 16 -
Revision 1.3
November 2009










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