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PDF ( 数据手册 , 数据表 ) CE5037

零件编号 CE5037
描述 Digital Satellite Tuner
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


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CE5037 数据手册, 描述, 功能
CE5037
Digital Satellite Tuner
with RF Bypass
Data Sheet
Features
• Direct conversion tuner for quadrature down
conversion from L-band to Zero IF
• Symbol rate 1-45 MS/s
• High sensitivity < -83 dBm at 27.5 MS/s Code rate
7/8
• Independent RF AGC and baseband gain control
• Fifth order baseband filters with bandwidth
adjustable from 6 to 43 MHz
• Fully integrated alignment-free low phase noise
local oscillator
• Selectable RF Bypass
• Low power consumption 0.5W at 3.3V.
• 28 pin 5x5 mm QFN Package
Applications
• DVB-S PayTV satellite receivers
• DSS satellite receivers
• DVB-S2 8PSK satellite receivers
January 2007
Ordering Information
WGCE5037 882557
28 Pin QFN* Trays
WGCE5037 S L9FV 882558 28 Pin QFN* Tape & Reel
*Pb Free Matte Tin
-10°C to +85°C
Description
The CE5037 is a fully integrated direct conversion
tuner for digital satellite receiver systems. It provides
excellent immunity to composite undesired channels.
The device also contains a RF Bypass for connecting
to a second receiver module.
The CE5037 is simple to use, requiring no alignment or
tuning algorithms and uses a minimum number of
external components. The device is programmable via
a I2C compatible bus.
The CE5037 is qualified for DVB-S2 8PSK receiver
applications
A complete reference design (CE9542) is available
using CE6313 demodulator.
RF Input
CE5037
Bypass
Output
Quadrature
VCO
PLL
RF AGC
I
Q
I2C
Control
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Loop
Filter
Crystal
Figure 1 - Basic Block Diagram
1
Intel Corporation
Order Number: D55745-002
Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright © 2007 Intel Corporation. All rights reserved.







CE5037 pdf, 数据表
CE5037
Data Sheet
2.0 Register Map and Programming
The register map is arranged as 16 byte-wide read/write registers grouped by functional block. The registers may
be written to and read-back from either sequentially (for lowest overhead) or specifically (for maximum flexibility).
A significant number of bits are used for test and evaluation purposes only and are fixed at logic ‘0’ or ‘1’. The
correct programming for these test bits is shown in the table below. It is essential that these values are programmed
for correct operation. When the contents of the registers are read back the value of some bits may have changed
from their programmed value. This is due to the internal automatic control which can update registers. Any changes
can be ignored.
Read only bits are marked with an asterisk (*). Any data written to these bits will be ignored.
Registers are set to default settings on applying power. These conditions are shown below and in the applicable
tables.
Register
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Block
PLL
PLL
PLL
PLL
RF Front End
Base Band
Base Band
Base Band
Local Oscillator
Local Oscillator
Local Oscillator
Local Oscillator
Local Oscillator
Local Oscillator
Local Oscillator
General
X* denotes a read only test bit
Function
PLF
214
213
212
211
27 26 25 24 23
0 0 C1 C0 R3
X* 1 0 0 0
X* 1 1 0 1
BF7 BF6 BF5 BF4 BF3
0 LF SF BR4 BR3
BLF* BG3 BG2 BG1 BG0
FLF*
0
1
0
0
10100
11110
X* X*
1
1
1
11010
X* X* X*
1
0
X* X*
1
1
0
PD CLR P0 0 X*
Table 2 - Register Map
210
22
R2
0
1
BF2
BR2
0
0
0
0
0
0
0
0
X*
29
21
R1
0
LEN
BF1
BR1
0
0
1
0
0
0
0
0
X*
28
20
R0
0
RFG
BF0
BR0
0
0
0
1
0
0
0
0
X*
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Intel Corporation







CE5037 equivalent, schematic
CE5037
Data Sheet
3.1 General Design Guidelines
Figure 4 shows a typical application using a CE6313 as a demodulator. This is available as a reference design
(CE9542) from Intel Corporation.
The design uses a standard two layer board. All components are mounted on the upper surface with the lower
surface as a ground plane. The RF input requires a coupling capacitor and series inductor for optimum matching.
The RF bypass output requires a coupling capacitor. Good decoupling should be used - these components should
be mounted as close to the device as practicable.
All ground contact to the CE5037 is to the ground ‘paddle’ on the underside of the package. This must be soldered
fully to the board to achieve best thermal and electrical contact. It is recommended that an array of vias (4 x 4) is
used to achieve good contact to the ground plane underneath the device
A common crystal reference can be used for the tuner and demodulator. The crystal oscillator capacitors are
optimised for a 10.111 MHz reference.
Sensitivity is optimised by minimizing interaction from digital signal activity in the demodulator. This is achieved by
filtering in the agc control, and filter networks in the baseband I and Q signals between the demodulator and
CE5037. These networks should be mounted as close to the CE5037 as possible.
The typical performance from the reference design is shown in the table below:
Parameter
Typ.
Units
Notes
Sensitivity
-83 dBm QEF 27.5MS/s rate 7/8
No added noise
C/N 27.5MS/s rate 7/8
2e-4 post Viterbi BER
8.3 dB Input = -69 dBm
8.1 dB
-45 dBm
8.1 dB
-23 dBm
C/N 2MS/s rate 7/8
2e-4 post Viterbi BER
8.2 dB Input = -81dBm
8.0 dB
-45 dBm
8.0 dB
-23 dBm
Interference Rejection Ratio
27.5 MS/s rate 7/8.
Interferers at -25 dBm
32
35
45
35
dB N+1
dB N+4
dB N+10
dB 2 Interferers at -25dBm
Table 23 - Typical Performance using CE5037 and CE6313
Further information is provided in CE9542 user guides.
The CE5037 can also be used with other demodulators. If the demodulator has a single-ended input then the
CE5037 can be used with a single-ended outputs ie IOUT and QOUT. The unused outputs should be loaded with
an equivalent load to the demodulator input to maintain a good balanced configuration. The optimum output level
for the demodulator can be achieved by adjusting the post filter baseband gain.
3.2 DVB-S2 Applications
The excellent performance of the CE5037 makes the device also suitable for the higher level modulation schemes
(8PSK) used for DVB-S2. In the critical areas of quadrature accuracy and phase noise, typical performance is
wwws.DhaotwaSnhienett4hUe.fcoolmlowing table.
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Intel Corporation










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