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PDF ( 数据手册 , 数据表 ) CY14B256Q2

零件编号 CY14B256Q2
描述 256-Kbit (32 K X 8) Serial (SPI) nvSRAM
制造商 Cypress Semiconductor
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CY14B256Q2 数据手册, 描述, 功能
CY14B256Q1
CY14B256Q2
CY14B256Q3
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
Features
256-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 32 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
(except for CY14B256Q1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
High-speed serial peripheral interface (SPI)
40-MHz clock rate
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4,1/2, or entire array
Low power consumption
Single 3 V +20%, –10% operation
Average active current of 10 mA at 40-MHz operation
Logic Block Diagram
Industry standard configurations
Industrial temperature
CY14B256Q1 has identical pin configuration to industry
standard 8-pin NV memory
8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14B256Q1/CY14B256Q2/CY14B256Q3
combines a 256-Kbit nvSRAM[1] with a nonvolatile element in
each memory cell with serial SPI interface. The memory is
organized as 32 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cell provides highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down
(except for CY14B256Q1). On power-up, data is restored to the
SRAM from the nonvolatile memory (RECALL operation). The
STORE and RECALL operations can also be initiated by the user
through SPI instruction.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B256Q1
No
Yes
CY14B256Q2
Yes
Yes
No No
CY14B256Q3
Yes
Yes
Yes
VCC
VCAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
32 K X 8
SRAM Array
32 K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
HSB
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SI
Instruction
register
Address
Decoder
A0-A14
D0-D7
Data I/O register
SO
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53882 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 24, 2011
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CY14B256Q2 pdf, 数据表
CY14B256Q1
CY14B256Q2
CY14B256Q3
SPI Operating Features
Power-Up
Power-up is defined as the condition when the power supply is
turned on and VCC crosses Vswitch voltage. During this time, the
CS must be allowed to follow the VCC voltage. Therefore, CS
must be connected to VCC through a suitable pull-up resistor. As
a built in safety feature, CS is both edge sensitive and level
sensitive. After power-up, the device is not selected until a falling
edge is detected on CS. This ensures that CS must have been
HIGH, before going LOW to start the first operation.
As described earlier, nvSRAM performs a Power-Up RECALL
operation after power-up and therefore, all memory accesses are
disabled for tFA duration after power-up. The HSB pin can be
probed to check the Ready or Busy status of nvSRAM after
power-up.
Power On Reset
A power on reset (POR) circuit is included to prevent inadvertent
writes. At power-up, the device does not respond to any
instruction until the VCC reaches the POR threshold voltage
(VSWITCH). After VCC transitions the POR threshold, the device
is internally reset and performs an Power-Up RECALL operation.
During Power-Up RECALL all device accesses are inhibited.
The device is in the following state after POR:
Deselected (after power-up, a falling edge is required on CS
before any instructions are started).
Standby power mode
Not in the HOLD condition
Status Register state:
Write Enable (WEN) bit is reset to ‘0’.
WPEN, BP1, BP0 unchanged from previous STORE
operation
Don’t care bits 4-6 are reset to ‘0’.
The WPEN, BP1, and BP0 bits of the Status Register are
nonvolatile bits and remain unchanged from the previous
STORE operation.
Before selecting and issuing instructions to the memory, a valid
and stable VCC voltage must be applied. This voltage must
remain valid until the end of the instruction transmission.
Power-Down
At power-down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
received when the power goes down, it is allowed tDELAY time to
complete the write. After this, all memory accesses are inhibited
and a conditional AutoStore operation is performed (AutoStore is
not performed if no writes have happened since the last RECALL
wwwcy.Dcleat)a. SThheisetf4eUat.ucoremprevents inadvertent writes to nvSRAM from
happening during power-down.
However, to completely avoid the possibility of inadvertent writes
during power-down, ensure that the device is deselected and is
in standby power mode, and the CS follows the voltage applied
on VCC.
Active Power and Standby Power Modes
When CS is LOW, the device is selected and is in the active
power mode. The device consumes ICC current, as specified in
DC Electrical Characteristics on page 15. When CS is HIGH, the
device is deselected and the device goes into the standby power
mode if a STORE or RECALL cycle is not in progress. If a
STORE or RECALL cycle is in progress, the device goes into the
standby power mode after the STORE or RECALL cycle is
completed. In the standby power mode, the current drawn by the
device drops to ISB.
SPI Functional Description
The CY14B256Q1/CY14B256Q2/CY14B256Q3 uses an 8-bit
instruction register. Instructions and their operation codes are
listed in Table 2. All instructions, addresses, and data are
transferred with the MSB first and start with a HIGH to LOW CS
transition. There are, in all, 10 SPI instructions that provide
access to most of the functions in nvSRAM. Further, the WP,
HOLD and HSB pins provide additional functionality driven
through hardware.
Table 2. Instruction Set
Instruction
Category
Status Register
control
instructions
SRAM
Read/Write
instructions
Special NV
instructions
Reserved
Instruction
Name
Opcode
Operation
WREN
0000 0110 Set write enable
latch
WRDI
0000 0100 Reset write
enable latch
RDSR
0000 0101 Read Status
Register
WRSR
0000 0001 Write Status
Register
READ
0000 0011 Read data from
memory array
WRITE 0000 0010 Write data to
memory array
STORE 0011 1100 Software STORE
RECALL 0110 0000 Software
RECALL
ASENB 0101 1001 AutoStore Enable
ASDISB 0001 1001 AutoStore Disable
- Reserved - 0001 1110
The SPI instructions are divided based on their functionality in
the following types:
Status Register access: RDSR and WRSR instructions
Write protection functions: WREN and WRDI instructions
along with WP pin and WEN, BP0, and BP1 bits
SRAM memory access: READ and WRITE instructions
nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
Document Number: 001-53882 Rev. *E
Page 8 of 26
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CY14B256Q2 equivalent, schematic
CY14B256Q1
CY14B256Q2
CY14B256Q3
Data Retention and Endurance
Parameter
DATAR
NVC
Capacitance
Description
Data retention
Nonvolatile STORE operations
Parameter[4]
Description
CIN
COUT
Input capacitance
Output pin capacitance
Thermal Resistance
Test Conditions
TA = 25 °C, f = 1 MHz,
VCC = VCC (Typ)
Parameter [4]
ΘJA
ΘJC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
Figure 18. AC Test Loads and Waveforms
3.0 V
OUTPUT
30 pF
577 Ω
R1
R2
789 Ω
3.0 V
OUTPUT
5 pF
Min
20
1,000
Unit
Years
K
Max Unit
6 pF
8 pF
16-SOIC
55.17
2.64
8-DFN
17.7
18.8
Unit
°C/W
°C/W
577 Ω
R1
R2
789 Ω
AC Test Conditions
Input pulse levels.................................................... 0 V to 3 V
Input rise and fall times (10% to 90%)......................... < 3 ns
Input and output timing reference levels........................ 1.5 V
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Note
4. These parameters are guaranteed by design and are not tested.
Document Number: 001-53882 Rev. *E
Page 16 of 26
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