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PDF ( 数据手册 , 数据表 ) CY14B256P

零件编号 CY14B256P
描述 256-Kbit (32 K X 8) Serial (SPI)
制造商 Cypress Semiconductor
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CY14B256P 数据手册, 描述, 功能
CY14B256P
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
with Real Time Clock
Features256-Kbit (32 K × 8) Serial (SPI) nvSRAM with Real Time Clock
256-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 32 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Real time clock (RTC)
Full-featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Backup current of 0.35 µA (typical)
High-speed serial peripheral interface (SPI)
40-MHz clock rate – SRAM memory access
25-MHz clock rate – RTC memory access
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Logic Block Diagram
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Single 3 V +20%, –10% operation
Average active current of 10 mA at 40 MHz operation
Industry standard configurations
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14B256P combines a 256-Kbit nvSRAM[1] with
a full-featured real time clock in a monolithic integrated circuit
with serial SPI interface. The memory is organized as 32 K words
of 8 bits each. The embedded nonvolatile elements incorporate
the QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
The STORE and RECALL operations can also be initiated by the
user through SPI instruction.
VCC
VCAP
CS
WP
SCK
HOLD
www.DataSheet4U.com
SI
Instruction decode
Write protect
Control logic
QuantumTrap
32 K X 8
SRAM Array
32 K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
Instruction
register
Address
Decoder
A0-A14
D0-D7
Data I/O register
RTC
MUX
Status Register
HSB
Xout
X in
INT
SO
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53881 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 19, 2011
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CY14B256P pdf, 数据表
CY14B256P
SPI Operating Features
Power-Up
Power-up is defined as the condition when the power supply is
turned on and VCC crosses Vswitch voltage. During this time, the
CS must be enabled to follow the VCC voltage. Therefore, CS
must be connected to VCC through a suitable pull-up resistor. As
a built in safety feature, CS is both edge-sensitive and
level-sensitive. After power-up, the device is not selected until a
falling edge is detected on CS. This ensures that CS must have
been HIGH, before going LOW to start the first operation.
As described earlier, nvSRAM performs a Power-Up RECALL
operation after power-up and therefore, all memory accesses are
disabled for tFA duration after power-up. The HSB pin can be
probed to check the Ready/Busy status of nvSRAM after
power-up.
Power On Reset
A power on reset (POR) circuit is included to prevent inadvertent
writes. At power-up, the device does not respond to any
instruction until the VCC reaches the POR threshold voltage
(VSWITCH). After VCC transitions the POR threshold, the device
is internally reset and performs an Power-Up RECALL operation.
During Power-Up RECALL all device accesses are inhibited.
The device is in the following state after POR:
Deselected (after power-up, a falling edge is required on CS
before any instructions are started).
Standby power mode
Not in the HOLD condition
Status Register state:
Write enable (WEN) bit is reset to ‘0’.
WPEN, BP1, BP0 unchanged from previous STORE
operation
Don’t care bits 4-6 are reset to ‘0’.
The WPEN, BP1, and BP0 bits of the Status Register are
nonvolatile bits and remain unchanged from the previous
STORE operation.
Prior to selecting and issuing instructions to the memory, a valid
and stable VCC voltage must be applied. This voltage must
remain valid until the end of the instruction transmission.
Power-Down
At power-down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
recieved when the power goes down, it is allowed tDELAY time to
complete the write. After this, all memory accesses are inhibited
and a conditional AutoStore operation is performed (AutoStore is
not performed if no writes have happened since the last RECALL
wwwcy.Dcleat)a. SThheisetf4eUat.ucoremprevents inadvertent writes to nvSRAM from
happening during power-down.
However, to avoid the possibility of inadvertent writes during
power-down, ensure that the device is deselected and is in
standby power mode, and the CS follows the voltage applied on
VCC.
Active Power and Standby Power Modes
When CS is LOW, the device is selected and is in the active
power mode. The device consumes ICC current, as specified in
DC Electrical Characteristics on page 25. When CS is HIGH, the
device is deselected and the device goes into the standby power
mode if a STORE or RECALL cycle is not in progress. If a
STORE/RECALL cycle is in progress, the device goes into the
standby power mode after the STORE/RECALL cycle is
completed. In the standby power mode, the current drawn by the
device drops to ISB.
SPI Functional Description
The CY14B256P uses an 8-bit instruction register. Instructions
and their operation codes are listed in Table 2. All instructions,
addresses, and data are transferred with the MSB first and start
with a HIGH to LOW CS transition. There are, in all, 12 SPI
instructions that provide access to most of the functions in
nvSRAM. Further, the WP, HOLD and HSB pins provide
additional functionality driven through hardware.
Table 2. Instruction Set
Instruction Instruction
Category
Name
WREN
Status
Register
instructions
WRDI
RDSR
WRSR
SRAM
read/write
instructions
READ
WRITE
RTC
read/write
instructions
RDRTC
WRTC
Special NV
instructions
Reserved
STORE
RECALL
ASENB
ASDISB
- Reserved -
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
0001 0011
0001 0010
0011 1100
0110 0000
0101 1001
0001 1001
0001 1110
Operation
Set write enable
latch
Reset write
enable latch
Read Status
Register
Write Status
Register
Read data from
memory array
Write data to
memory array
Read RTC
registers
Write RTC
registers
Software STORE
Software
RECALL
AutoStore enable
AutoStore disable
The SPI instructions in CY14B256P are divided based on their
functionality in the following types:
Status Register access: RDSR and WRSR instructions
Write protection functions: WREN and WRDI instructions
along with WP pin and WEN, BP0, and BP1 bits
SRAM memory access: READ and WRITE instructions
RTC access: RDRTC and WRTC instructions
nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
Document Number: 001-53881 Rev. *E
Page 8 of 36
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CY14B256P equivalent, schematic
CY14B256P
Real Time Clock Operation
nvTime Operation
The CY14B256P offers internal registers that contain clock,
alarm, watchdog, interrupt, and control functions. The RTC
registers occupy a separate address space from nvSRAM and
are accessible through Read RTC (RDRTC) and Write RTC
(WRTC) instructions on register addresses 0x00 to 0x0F. Internal
double buffering of the clock and the timer information registers
prevents accessing transitional internal clock data during a read
or write operation. Double buffering also circumvents disrupting
normal timing counts or the clock accuracy of the internal clock
when accessing clock data. Clock and alarm registers store data
in BCD format.
Clock Operations
The clock registers maintain time up to 9,999 years in
one-second increments. The time can be set to any calendar
time and the clock automatically keeps track of days of the week
and month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. The user must stop
internal updates to the CY14B256P time keeping registers
before reading clock data, to prevent reading of data in transition.
Stopping the register updates does not affect clock accuracy.
The updating process is stopped by writing a ‘1’ to the read bit
‘R’ (in the flags register at 0x00), and does not restart until a ‘0’
is written to the read bit. The RTC registers are read while the
internal clock continues to run. After a ‘0’ is written to the read bit
(‘R’), all RTC registers are simultaneously updated within 20 ms.
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x00) to a ‘1’ stops
updates to the time keeping registers and enables the time to be
set. The correct day, date, and time is then written into the
registers and must be in 24-hour BCD format. The time written
is referred to as the “Base Time”. This value is stored in
nonvolatile registers and used in the calculation of the current
time. Resetting the write bit to ‘0’ transfers the values of
timekeeping registers to the actual clock counters, after which
the clock resumes normal operation.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue
counting to 0xF before rolling over to 0x0 after which RTC
resumes normal operation.
wwwN.oDteataASfhteerett4hUe.coWm’ bit is set to ‘0’, values written into the
timekeeping, alarm, calibration, and interrupt registers are
transfered to the RTC time keeping counters in tRTCp time. These
counter values must be saved to nonvolatile memory either by
initiating a Software/Hardware STORE or AutoStore operation.
While working in AutoStore disabled mode, perform a STORE
operation after tRTCp time while writing into the RTC registers for
the modifications to be correctly recorded.
Backup Power
The RTC in the CY14B256P is intended for permanently
powered operation. The VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When the primary power, VCC, fails and drops below
VSWITCH the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14B256P consumes 0.35 µA
(typical) at room temperature. The user must choose capacitor
or battery values according to the application.
Backup time values based on maximum current specifications
are shown in the following table. Nominal backup times are
approximately two times longer.
Table 8. RTC Backup Time
Capacitor Value
0.1 F
0.47 F
1.0 F
Backup Time
72 hours
14 days
30 days
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3-V lithium is recommended and the CY14B256P
sources current only from the battery when the primary power is
removed. However, the battery is not recharged at any time by
the CY14B256P. The battery capacity must be chosen for the
total anticipated cumulative down time required over the life of
the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x08 controls the
enable and disable of the oscillator. This bit is nonvolatile and is
shipped to customers in the “enabled” (set to ‘0’) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
While system power is off, if the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum level,
the oscillator may fail. The CY14B256P has the ability to detect
oscillator failure when system power is restored. This is recorded
in the oscillator fail flag (OSCF) of the flags register at the
address 0x00. When the device is powered on (VCC goes above
VSWITCH) the OSCEN bit is checked for “enabled” status. If the
OSCEN bit is enabled and the oscillator is not active within the
first 5 ms, the OSCF bit is set to ‘1’. The system must check for
this condition and then write ‘0’ to clear the flag. Note that in
addition to setting the OSCF flag bit, the time registers are reset
to the “Base Time” (see Setting the Clock on page 16), which is
the value last written to the timekeeping registers. The control or
calibration registers and the OSCEN bit are not affected by the
‘oscillator failed’ condition.
Document Number: 001-53881 Rev. *E
Page 16 of 36
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