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PDF ( 数据手册 , 数据表 ) ADF7241

零件编号 ADF7241
描述 Low Power IEEE 802.15.4 Zero-IF 2.4 GHz Transceiver IC
制造商 Analog Devices
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ADF7241 数据手册, 描述, 功能
Low Power IEEE 802.15.4 Zero-IF 2.4 GHz
Transceiver IC
ADF7241
FEATURES
Frequency range (global ISM band)
2400 MHz to 2483.5 MHz
IEEE 802.15.4-2006-compatible (250 kbps)
Low power consumption
19 mA (typical) in receive mode
21.5 mA (typical) in transmit mode (PO = 3 dBm)
1.7 μA, 32 kHz crystal oscillator wake-up mode
High sensitivity
−95 dBm at 250 kbps
Programmable output power
−20 dBm to +4.8 dBm in 2 dB steps
Integrated voltage regulators
1.8 V to 3.6 V input voltage range
Excellent receiver selectivity and blocking resilience
Zero-IF architecture
Complies with EN300 440 Class 2, EN300 328, FCC CFR47
Part 15, ARIB STD-T66
Digital RSSI measurement
Fast automatic VCO calibration
Automatic RF synthesizer bandwidth optimization
On-chip low power processor performs
Radio control
Packet management
Packet management support
Insertion/detection of preamble address/SFD/FCS
IEEEE 802.15.4-2006 frame filtering
IEEEE 802.15.4-2006 CSMA/CA unslotted modes
Flexible 256-byte transmit/receive data buffer
SPORT mode
Flexible multiple RF port interface
External PA/LNA support hardware
Switched antenna diversity support
Wake-up timer
Very few external components
Integrated PLL loop filter, receive/transmit switch, battery
monitor, temperature sensor, 32 kHz RC and crystal
oscillators
Flexible SPI control interface with block read/write access
Small form factor 5 mm × 5 mm 32-lead LFCSP package
APPLICATIONS
Wireless sensor networks
Automatic meter reading/smart metering
Industrial wireless control
Healthcare
Wireless audio/video
Consumer electronics
ZigBee
ADF7241
LNA1
LNA2
FUNCTIONAL BLOCK DIAGRAM
DAC
ADC
ADC
DAC
DSSS
DEMOD
AGC
OCL
CDR
8-BIT
PROCESSOR
RADIO
CONTROLLER
PACKET
MANAGER
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PA
LDO × 4
FRACTIONAL-N
RF SYNTHESIZER
PRE-EMPHASIS FILTER
WAKE-UP CTRL
BIAS
BATTERY TEMPERATURE
MONITOR
SENSOR
26MHz
OSC
32kHz
RC
OSC
32kHz
XTAL
OSC
4kB
PROGRAM
ROM
2kB
PROGRAM
RAM
256-BYTE
PACKET
RAM
64-BYTE
BBRAM
256-BYTE
MCR
SPI
GPIO
SPORT
IRQ
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.







ADF7241 pdf, 数据表
ADF7241
AUXILIARY SPECIFICATIONS
Table 5.
Parameter
32 kHz RC OSCILLATOR
Frequency
Frequency Accuracy
Frequency Drift
Temperature Coefficient
Voltage Coefficient
Calibration Time
32 kHz CRYSTAL OSCILLATOR
Frequency
Maximum ESR
Start-Up Time
WAKE-UP TIMER
Prescaler Tick Period
Wake-Up Period
TEMPERATURE SENSOR
Range
Resolution
Accuracy
Min Typ
32.768
1
0.14
4
1
32.768
319.8
2000
0.0305
61 × 10−6
−40
4.7
±6.4
BATTERY MONITOR
Trigger Voltage
Trigger Voltage Step Size
Start-Up Time
Current Consumption
EXTERNAL PA INTERFACE
RON, PAVSUP_ATB3 to VDD_BAT
ROFF, PAVSUP_ATB3 to GND
ROFF, PABIASOP_ATB4 to GND
PABIASOP_ATB4 Source Current, Maximum
PABIASOP_ATB4 Sink Current, Minimum
PABIASOP_ATB4 Current Control Resolution
PABIASOP_ATB4 Compliance Voltage
PABIASOP_ATB4 Compliance Voltage
Servo Loop Bias Current
Servo Loop Bias Current Control Step
1.7
62
5
30
5
10
10
80
−80
6
150
3.45
22
0.349
Max Unit Test Conditions
kHz After calibration
% After calibration at 25°C
%/°C
%/V
ms
kHz
kΩ 10 pF on XOSC32KP and XOSC32KN
ms 12.5 pF load capacitors on XOSC32KP and
XOSC32KN
20,000 ms
1.31 × 105 sec
+85 °C
°C
°C Average of 1000 ADC readbacks, after
using linear fitting, with correction at
known temperature
3.6 V
mV
μs
μA
Ω extpa_bias_mode = 0, 1, 2, 5, 6
MΩ extpa_bias_mode = 3, 4, power-down
MΩ extpa_bias_mode = 0, power-down
μA expta_bias_mode = 1, 3
μA extpa_bias_mode = 2, 4
Bits extpa_bias_mode = 1, 2, 3, 4, 5
mV extpa_bias_mode = 2, 4
V extpa_bias_mode = 1, 3
mA extpa_bias_mode = 5, 6
mA extpa_bias_mode = 5, 6
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Rev. 0 | Page 8 of 72







ADF7241 equivalent, schematic
ADF7241
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CREGRF1 1
RBIAS 2
CREGRF2 3
RFIO1P 4
RFIO1N 5
RFIO2P 6
RFIO2N 7
CREGRF3 8
ADF7241
TOP VIEW
(Not to Scale)
24 CS
23 MOSI
22 SCLK
21 MISO
20 IRQ1_GP4
19 TRCLK_CKO_GP3
18 IRQ2_TRFS_GP2
17 DT_GP1
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED TO GROUND.
Figure 10. Pin Configuration
Table 16. Pin Function Descriptions
Pin No. Mnemonic
Description
1 CREGRF1
Regulated Supply Terminal for RF Section. Connect a 220 nF decoupling capacitor from this pin to
GND.
2 RBIAS
Bias Resistor 27 kΩ to Ground.
3 CREGRF2
Regulated Supply for RF Section. Connect a 100 pF decoupling capacitor to ground.
4 RFIO1P
Differential RF Input Port 1 (Positive Terminal). A 10 nF coupling capacitor is required.
5 RFIO1N
Differential RF Input Port 1 (Negative Terminal). A 10 nF coupling capacitor is required.
6 RFIO2P
Differential RF Input/Output Port 2 (Positive Terminal). A 10 nF coupling capacitor required.
7 RFIO2N
Differential RF Input/Output Port 2 (Negative Terminal). A 10 nF coupling capacitor required.
8 CREGRF3
Regulated Supply for RF Section. Connect a 100 pF decoupling capacitor from this pin to GND.
9 CREGVCO
Regulated Supply for VCO Section. Connect a 220 nF decoupling capacitor from this pin to GND.
10 VCOGUARD
Guard Trench for VCO Section. Connect to Pin 9 (CREGVCO).
11 CREGSYNTH
Regulated Supply for PLL Section. Connect a 220 nF decoupling capacitor from this pin to GND.
12 XOSC26P
Terminal 1 of External Crystal and Loading Capacitor. This pin is no connect (NC) when an external
oscillator is used.
13 XOSC26N
Terminal 2 of External Crystal and Loading Capacitor. Input for external oscillator.
14 DGUARD
Guard Trench for Digital Section. Connect to Pin 15 (CREGDIG2).
15 CREGDIG2
Regulated Supply for Digital Section. Connect a 220 nF decoupling capacitor to ground.
16 DR_GP0
SPORT Receive Data Output/General-Purpose IO Port.
17 DT_GP1
SPORT Transmit Data Input/General-Purpose IO Port.
18
IRQ2_TRFS_GP2
Interrupt Request Output 2/IEEE 802.15.4-2006 Symbol Clock/General-Purpose IO Port.
19
TRCLK_CKO_GP3
SPORT Clock Output/General-Purpose IO Port.
20 IRQ1_GP4
Interrupt Request Output 1/General-Purpose IO Port.
21 MISO
SPI Interface Serial Data Output.
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SPI Interface Data Clock Input.
23 MOSI
SPI Interface Serial Data Input.
24 CS
SPI Interface Chip Select Input (and Wake-Up Signal).
25 TXEN_GP5
External PA Enable Signal/General-Purpose IO Port.
26 RXEN_GP6
External LNA Enable Signal/General-Purpose IO Port.
27 CREGDIG1
Regulated Supply for Digital Section. Connect a 1 nF decoupling capacitor from this pin to ground.
28 XOSC32KP_GP7_ATB1 Terminal 1 of 32 kHz Crystal Oscillator/General-Purpose IO Port/Analog Test Bus 1.
29
XOSC32KN_ATB2
Terminal 2 of 32 kHz Crystal Oscillator/Analog Test Bus 2.
Rev. 0 | Page 16 of 72










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