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PDF ( 数据手册 , 数据表 ) 64F7055

零件编号 64F7055
描述 HD64F7055
制造商 Renesas Technology
LOGO Renesas Technology LOGO 


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64F7055 数据手册, 描述, 功能
To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
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64F7055 pdf, 数据表
Page Item
Revisions (See Manual for Details)
800 24.3.1 Transition to Hardware Description added:
Standby Mode
“...when the HSTBY and RES pins go low.”
819, 821, Table 25.4 DC Characteristics
822
Amended and added to :
Maximum value of input high-level voltage for RES,
NMI, FWE, MD2–MD0, and HSTBY pins amended to
5.8 V
“When memory is expanded externally” amended to
“When in MCU expansion mode”.
Characteristic values of input high-level voltage, input
leak current, output high-level voltage, and output
low-level voltage for PE15–PE0, PF15–PF0, and
PH15–PH0 (when in MCU expansion mode) added.
Minimum value of input high-level voltage for
AUDRST and AUDMD pins amended to VCC–0.5.
Measurement conditions of input leak current for
D15–D0, WAIT, and BREQ pins amended
(Vin = 0.5 V to PVCC1–0.5 V).
BACK pin added to the three-state leak current (while
OFF) and content regarding the minimum value
removed.
BACK pin added to the output high-level voltage
825 25.3 AC Characteristics
25.3.1 Timing for swicthing the power supply on/off
added.
Table 25.6 Timing for swicthing the power supply
on/off added.
Figure 25.1 Power-On/Off Timing added
Hence the following sections, clause numbers table
numbers, and figure numbers have been changed
(section 25).
849 Figure 25.28 Output Test Circuit Directions of diodes in the figure depiching an output
test circuit have been amended
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64F7055 equivalent, schematic
Section 14 Compare Match Timer (CMT) ................................................................... 447
14.1 Overview............................................................................................................................ 447
14.1.1 Features ................................................................................................................ 447
14.1.2 Block Diagram...................................................................................................... 448
14.1.3 Register Configuration ......................................................................................... 449
14.2 Register Descriptions......................................................................................................... 450
14.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 450
14.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 451
14.2.3 Compare Match Timer Counter (CMCNT).......................................................... 452
14.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 453
14.3 Operation ........................................................................................................................... 453
14.3.1 Cyclic Count Operation........................................................................................ 453
14.3.2 CMCNT Count Timing ........................................................................................ 454
14.4 Interrupts............................................................................................................................ 454
14.4.1 Interrupt Sources and DTC Activation................................................................. 454
14.4.2 Compare Match Flag Set Timing ......................................................................... 454
14.4.3 Compare Match Flag Clear Timing...................................................................... 455
14.5 Usage Notes ....................................................................................................................... 456
14.5.1 Contention between CMCNT Write and Compare Match ................................... 456
14.5.2 Contention between CMCNT Word Write and Incrementation .......................... 457
14.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 458
Section 15 Serial Communication Interface (SCI) .................................................... 459
15.1 Overview............................................................................................................................ 459
15.1.1 Features ................................................................................................................ 459
15.1.2 Block Diagram...................................................................................................... 460
15.1.3 Pin Configuration ................................................................................................. 461
15.1.4 Register Configuration ......................................................................................... 462
15.2 Register Descriptions......................................................................................................... 463
15.2.1 Receive Shift Register (RSR)............................................................................... 463
15.2.2 Receive Data Register (RDR) .............................................................................. 464
15.2.3 Transmit Shift Register (TSR).............................................................................. 464
15.2.4 Transmit Data Register (TDR) ............................................................................ 465
15.2.5 Serial Mode Register (SMR)................................................................................ 465
15.2.6 Serial Control Register (SCR).............................................................................. 468
15.2.7 Serial Status Register (SSR)................................................................................. 472
15.2.8 Bit Rate Register (BRR)....................................................................................... 476
15.2.9 Serial Direction Control Register (SDCR) ........................................................... 483
15.2.10 Inversion of SCK Pin Signal ................................................................................ 484
15.3 Operation ........................................................................................................................... 484
15.3.1 Overview .............................................................................................................. 484
15.3.2 Operation in Asynchronous Mode........................................................................ 486
15.3.3 Multiprocessor Communication ........................................................................... 496
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