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PDF ( 数据手册 , 数据表 ) UT62L5128

零件编号 UT62L5128
描述 512K X 8 BIT LOW POWER CMOS SRAM
制造商 Utron technology
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UT62L5128 数据手册, 描述, 功能
Rev. 1.4
UTRON
REVISION HISTORY
UT62L5128
512K X 8 BIT LOW POWER CMOS SRAM
REVISION
Preliminary Rev. 0.5
Rev. 1.0
DESCRIPTION
Released DATE
Original.
Mar, 2001
1. The symbols CE# and OE# and WE# are revised as. CE and Jun 21,2001
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
OE and WE .
2. Separate Industrial and Consumer SPEC.
3. Add access time 55ns range.
Add STSOP package
Add SOP package
1. Revised 36-pin TFBGA package outline dimension
a Rev. 1.2 : ball diameter=0.3mm
b Rev. 1.3 : ball diameter=0.35mm
2. Revised DC ELECTRICAL CHARACTERISTICS
c Revised VIH as 2.2V
1. Revised Operation surrent :
-Icc(max) 45/35/25mA 40/30/25mA
-Icc(Typ) 30/25/20mA 30/20/16mA
2. Revised Standby current : 20/3uA 20/2uA
3. Revised VOH(Typ) : NA 2.7V
4. Add VIH(max)=VCC+2.0V for pulse width less than 10ns.
VIL(min)=VSS-2.0V for pulse width less than 10ns.
5. Revised AC Table tOHZ* characteristics
6. Add order information for lead free product
Aug 3,2001
Mar 25,2002
May 3,2002
May 8,2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
www.DataSheet.in
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UT62L5128 pdf, 数据表
Rev. 1.4
UTRON
UT62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Notes :
1. WE , CE must be high during all address transitions.
2.A write occurs during the overlap of a low CE , low WE .
3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
DATA RETENTION CHARACTERISTICS (TA = 0 to 70 / -20 to 80 (E))
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
SYMBOL
VDR
IDR
tCDR
tR
TEST CONDITION
CE VCC-0.2V
Vcc=1.5V
CE VCC-0.2V
See Data Retention
Waveforms (below)
MIN.
1.5
-L -
- LL -
0
5
TYP.
-
1
0.5
-
-
MAX.
3.6
50
20
-
-
UNIT
V
µA
µA
ms
ms
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform ( CE controlled)
VCC
CE
Vcc(min.)
tCDR
VIH
VDR 1.5V
CE VCC-0.2V
Vcc(min.)
tR
VIH
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
www.DataSheet.in
P80051














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