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PDF ( 数据手册 , 数据表 ) DAC1008D650

零件编号 DAC1008D650
描述 Dual 10-bit DAC up to 650 Msps
制造商 NXP Semiconductors
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DAC1008D650 数据手册, 描述, 功能
DAC1008D650
Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
with JESD204A interface
Rev. 1 — 1 October 2010
Preliminary data sheet
1. General description
The DAC1008D650 is a high-speed 10-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier WCDMA
transmitters.
Because of its digital on-chip modulation, the DAC1008D650 allows the complex pattern
provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to
IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit
Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1008D650 also includes a 2×, 4× or 8× clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the output full-scale
current.
The input data format is serial according to JESD204A specification. This new interface
has numerous advantages over the traditional parallel one: easy PCB layout, lower
radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum
number of lanes of the DAC1008D650 is 4 and its maximum serial data rate is
3.125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output
clock period between several DAC devices. MDS incorporates modes: Master/slave and
All slave mode.
2. Features and benefits
„ Dual 10-bit resolution
„ 650 Msps maximum update rate
„ Selectable 2×, 4× or 8× interpolation
filters
„ Input data rate up to 312.5 Msps
„ Very low noise cap free integrated PLL
„ 32-bit programmable NCO frequency
„ Four JESD204A serial input lanes
„ 1.8 V and 3.3 V power supplies
„ LVDS compatible clock inputs
„ IMD3: 76 dBc; fs = 640 Msps;
fo = 140 MHz
„ ACPR: 64 dBc; two carriers WCDMA;
fs = 640 Msps; fo = 133 MHz
„ Typical 1.20 W power dissipation at
4× interpolation, PLL off and 640 Msps
„ Power-down mode and Sleep modes
„ Differential scalable output current from
1.6 mA to 22 mA
„ On-chip 1.25 V reference
„ External analog offset control
(10-bit auxiliary DACs)
„ Internal digital offset control
„ Inverse (sin x) / x function
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DAC1008D650 pdf, 数据表
NXP Semiconductors
DAC1008D650
2×, 4× or 8× interpolating DAC with JESD204A
Table 5. Characteristics …continued
VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = 40 °C to +85 °C;
typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum
sample rate; PLL off unless otherwise specified.
Symbol
Parameter
Conditions
Test[1] Min Typ Max
Unit
Vidth
input differential
threshold voltage
|Vgpd| < 50 mV[4]
C
100 -
+100
mV
Ri input resistance
CI input capacitance
Digital inputs (SDO, SDIO, SCLK, SCS_N, RESET_N)
D
- 10 -
MΩ
D - 0.5 - pF
VIL LOW-level input
voltage
C
GND -
0.54 V
VIH HIGH-level input
voltage
C
1.26 -
VDDD
V
IIL
LOW-level input
VIL = 0.54 V
current
I
- 1-
μA
IIH
HIGH-level input
VIH = 1.26 V
current
I
- 1-
μA
Digital inputs (Vin_p/Vin_n)[5]
VI(cm)
common-mode input
voltage
D
0.68 0.78 1.40
V
VI(dif)(p-p)
peak-to-peak
differential input
voltage
D
175 -
1000
mV
Ztt Vtt source impedance
ΔZi differential input
impedance
D
- 0.7 -
Ω
D
- 100 -
Ω
Digital outputs (SYNC_OUTN/SYNC_OUTP)[6]
Vo(cm)
common-mode output
voltage
I
0.79 1.17 1.46
V
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
I
0.12 0.48 0.96
V
Digital inputs/outputs (MDS_N/MDS_P)
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
D
- 600 -
mV
Co(L)
Output load
capacitance
between pins GND and
MDS_N or MDS_P
D
-
- 10
pF
CI
Input capacitance
between pins GND and
D
- 0.3 -
pF
MDS_N or MDS_P
Analog outputs (IOUTAP, IOUTAN, IOUTBP, IOUTBN)
IO(fs)
full-scale output
current
register value = 00h
D
(see Table 14 and Table 15)
- 1.6 -
mA
register = default value
(see Table 14 and Table 15)
- 20 -
mA
VO
output voltage
compliance range
D
1.8 -
VDDA(3V3) V
Ro output resistance
D
- 250 -
kΩ
DAC1008D650
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 October 2010
© NXP B.V. 2010. All rights reserved.
8 of 98
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DAC1008D650 equivalent, schematic
NXP Semiconductors
DAC1008D650
2×, 4× or 8× interpolating DAC with JESD204A
After the initial ILA sequence, the lane alignment monitoring starts. When a K28.3 /A/
symbol is received among the user data:
its position is compared to the value of the alignment monitor counter
if two successive K28.3 /A/ symbols have been received at a wrong position, a
realignment takes place
if the buffers are empty or overflow, this is indicated by the registers
ILA_BUF_ERR_LN0 to ILA_BUF_ERR_LN3
10.2.5.2 Multi-device operation
DAC1008D650 implements a multi-device inter-lane alignment that guarantees a skew of
less than one output period between them.
Two modes are available: master/slave and all slave. Both make use of the MDS_P and
MDS_N pins.
LANES
ref_A
mds_A_out
COMP
mds_A
MDS_A
I
DIG BUFFER
Q
SYNC~
CLK
MGMT
DAC
CK
Fig 8. Multi-Device Synchronization (MDS) implementation
001aal073
Each DAC device of the system generates its own reference (ref_A in Figure 8).
If configured as a slave, an early-late comparator compares the internal reference with the
external reference provided by the MDS pins. The comparator controls an internal buffer
that is used to delay the samples.
DAC1008D650
Preliminary data sheet
www.DataSheet.in
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 October 2010
© NXP B.V. 2010. All rights reserved.
16 of 98










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