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PDF ( 数据手册 , 数据表 ) 26DF161

零件编号 26DF161
描述 AT26DF161
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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26DF161 数据手册, 描述, 功能
Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
66 MHz Maximum Clock Frequency
Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– Sixteen 128-Kbyte Physical Sectors
Hardware Controlled Locking of Protected Sectors
Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
Automatic Checking and Reporting of Erase/Program Failures
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 7 mA Active Read Current (Typical)
– 4 µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (200-mil wide)
1. Description
The AT26DF161 is a serial interface Flash memory device designed for use in a wide
variety of high-volume consumer based applications in which program code is shad-
owed from Flash memory into embedded or external RAM for execution. The flexible
erase architecture of the AT26DF161, with its erase granularity as small as 4-Kbytes,
makes it ideal for data storage as well, eliminating the need for additional data storage
EEPROM devices.
The physical sectoring and the erase block sizes of the AT26DF161 have been opti-
mized to meet the needs of today's code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
16-megabit
2.7-volt Only
Serial Firmware
DataFlash®
Memory
AT26DF161
For New
Designs Use
AT25DF161
3599H–DFLASH–8/09







26DF161 pdf, 数据表
8. Program and Erase Commands
8.1 Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of
data to be programmed into previously erased memory locations. An erased memory location is
one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page
Program command can be started, the Write Enable command must have been previously
issued to the device (see Write Enable command description) to set the Write Enable Latch
(WEL) bit of the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device
followed by the three address bytes denoting the first byte location of the memory array to begin
programming at. After the address bytes have been clocked in, data can then be clocked into the
device and will be stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page
boundary (A7-A0 are not all 0), then special circumstances regarding which memory locations
will be programmed will apply. In this situation, any data that is sent to the device that goes
beyond the end of the page will wrap around back to the beginning of the same page. For exam-
ple, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to
the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining
bytes in the page (addresses 000001h through 0000FDh) will be unaffected and will not change.
In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes
sent will be latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and pro-
gram it into the appropriate memory array locations based on the starting address specified by
A23-A0 and the number of complete data bytes sent to the device. If less than 256 bytes of data
were sent to the device, then the remaining bytes within the page will not be altered. The pro-
gramming of the data bytes is internally self-timed and should take place in a time of tPP.
The three address bytes and at least one complete byte of data must be clocked into the device
before the CS pin is deasserted; otherwise, the device will abort the operation and no data will
be programmed into the memory array. In addition, if the address specified by A23-A0 points to
a memory location within a sector that is in the protected state (see “Protect Sector” on page
12), then the Byte/Page Program command will not be executed, and the device will return to the
idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset
back to the logical “0” state if the program cycle aborts due to an incomplete address being sent,
an incomplete byte of data being sent, or because the memory location to be programmed is
protected.
While the device is programming, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled
rather than waiting the tPP time to determine if the data bytes have finished programming. At
some point before the program cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program correctly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.
8 AT26DF161
3599H–DFLASH–8/09







26DF161 equivalent, schematic
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro-
tect, then the system can simply write a 0Fh to the Status Register to change the SPRL bit from
a logical “1” to a logical “0” provided the WP pin is deasserted. Likewise, the system can write an
F0h to change the SPRL bit from a logical “0” to a logical “1” without affecting the current sector
protection status (no changes will be made to the Sector Protection Registers).
When writing to the Status Register, bits 5, 4, 3, and 2 will not actually be modified but will be
decoded by the device for the purposes of the Global Protect and Global Unprotect functions.
Only bit 7, the SPRL bit, will actually be modified. Therefore, when reading the Status Register,
bits 5, 4, 3, and 2 will not reflect the values written to them but will instead indicate the status of
the WP pin and the sector protection status. Please refer to the “Read Status Register” section
and Table 10-1 on page 19 for details on the Status Register format and what values can be
read for bits 5, 4, 3, and 2.
9.6 Read Sector Protection Registers
The Sector Protection Registers can be read to determine the current software protection status
of each sector. Reading the Sector Protection Registers, however, will not determine the status
of the WP pin.
To read the Sector Protection Register for a particular sector, the CS pin must first be asserted
and the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three address
bytes designating any address within the sector must be clocked in. After the last address byte
has been clocked in, the device will begin outputting data on the SO pin during every subse-
quent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote
the value of the appropriate Sector Protection Register
Table 9-3. Read Sector Protection Register – Output Data
Output Data
Sector Protection Register Value
00h Sector Protection Register value is 0 (sector is unprotected).
FFh Sector Protection Register value is 1 (sector is protected).
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
In addition to reading the individual Sector Protection Registers, the Software Protection Status
(SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are
software protected (please refer to “Status Register Commands” on page 19 for more details).
16 AT26DF161
3599H–DFLASH–8/09










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