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PDF ( 数据手册 , 数据表 ) D72042

零件编号 D72042
描述 UPD72042
制造商 NEC
LOGO NEC LOGO 


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D72042 数据手册, 描述, 功能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72042
LSI DEVICES FOR Inter Equipment BusTM (IEBusTM)
PROTOCOL CONTROL
The µPD72042 is a microcomputer peripheral LSI device for IEBus protocol control.
The µPD72042 performs all the processing required for layers 1 and 2 of the IEBus. The devices incorporate large
transmission and reception buffers, allowing the microcomputer to perform IEBus operations without interruption.
They also contain an IEBus driver and receiver, allowing them to directly connected to the bus directly.
FEATURES
Control of layers 1 and 2 of the IEBus protocol
• Support of a multi-master scheme
• Broadcast function
• Two communication modes having different
transmission speeds can be selected.
Mode 0
Mode 1
Transmission speed
Approx. 3.9 Kbps
Approx. 17 Kbps
q Built-in IEBus driver and receiver
q Transmission and reception buffers
Transmission buffer : 33 bytes, FIFO
Reception buffer
: 40 bytes, FIFO (capable of
holding more than one frame
of reception data.)
ORDERING INFORMATION
Microcomputer interface
Three-/two-wire serial I/O,
Transfer starting with MSB
Program crashes can be detected by means of a
watchdog timer.
Low power consumption (standby mode):
50 µA (max)
Oscillator frequency (fX): 6 MHz
• frequency accuracy: ±1.5%
Operating voltage: 5 V ±10%
Part number
µPD72042GT
Package
16-pin plastic SOP (9.53 mm (375))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S14870EJ1V0DS00 (1st edition)
Date Published June 2000 N CP(N)
Printed in Japan
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©
2000







D72042 pdf, 数据表
µPD72042
2. IEBus OPERATION
2.1 OVERVIEW
The µPD72042 is a CMOS LSI device for the IEBus interface.
The IEBus is designed to enable the data transmission between devices in a small-scale digital data transmission
system.
The µPD72042 is connected to a microcomputer built into a device. A serial interface (SCK, SO, and SI pins) is
used for connection. The host controller (microcomputer) sets the commands and data needed for data transmission
via this serial interface.
When data is transmitted, the host controller sets the data in the µPD72042 via the serial interface.
Then, signals are output on the BUS pins (BUS+, BUS–). When data is received from the BUS pins, the host controller
can read it via the serial interface.
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Data Sheet S14870EJ1V0DS00







D72042 equivalent, schematic
µPD72042
(7) Parity bit
A parity bit is used to check for errors in the transmission data.
A parity bit is added to the master address bits, slave address bits, control bits, data-length bits, and data bits.
Even parity is used. If the number of 1’s in the data is odd, the parity bit is set to 1. If the number of 1’s in the
data is even, the parity bit is set to 0.
(8) Acknowledge bit
In ordinary communication (one-unit-to-one-unit communication), an acknowledge bit is added in the following
positions to confirm that data has been received correctly:
• At the end of the slave address field
• At the end of the control field
• At the end of the data-length field
• At the end of the data field
The acknowledge bit is defined as follows:
• 0: Indicates that transmission data has been recognized. (ACK)
• 1: Indicates that no transmission data has been recognized. (NAK)
For broadcast, the acknowledge bit is ignored.
1 Acknowledge bit at the end of the slave address field
If any of the following is detected, the acknowledge bit at the end of the slave address field is set to NAK,
and transmission is stopped:
• The parity of the master address bits or slave address bits is incorrect.
• A timing error occurred (bit format error).
• No slave unit is found.
2 Acknowledge bit at the end of the control field
If any of the following is detected, the acknowledge bit at the end of the control field is set to NAK, and
transmission is stopped:
• The parity of the control bits is incorrect.
• Although the slave reception bufferNote is not empty, bit 3 of the control bits is 1 (write operation).
• Although the slave transmission bufferNote is empty, the control bits indicate data read (3H, 7H).
• For a locked unit, a unit other than the unit that specified the lock makes a request by using control bits
indicating 3H, 6H, 7H, AH, BH, EH, or FH.
• Although no lock has been set, control bits indicating lock address read (4H) are set.
• A timing error occurred.
• An undefined control bit setting has been made.
Note See (1) in Section 2.4.
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Data Sheet S14870EJ1V0DS00










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