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PDF ( 数据手册 , 数据表 ) 49LF002A

零件编号 49LF002A
描述 SST49LF002A
制造商 Silicon Storage Technology
LOGO Silicon Storage Technology LOGO 


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49LF002A 数据手册, 描述, 功能
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
www.DataSheet4U.com
SST49LF002A / 003A / 004A / 008A2 Mb / 3 Mb / 4 Mb / 8 Mb Firmware Hub for Intel 8xx Chipsets
FEATURES:
Advance Information
• Firmware Hub for Intel 8xx Chipsets
• 2 Mbit, 3 Mbit, 4 Mbit, or 8 Mbit SuperFlash
memory array for code/data storage
– SST49LF002A: 256K x8 (2 Mbit)
– SST49LF003A: 384K x8 (3 Mbit)
– SST49LF004A: 512K x8 (4 Mbit)
– SST49LF008A: 1024K x8 (8 Mbit)
• Flexible Erase Capability
– Uniform 4 KByte Sectors
– Uniform 16 KByte overlay blocks for
SST49LF002A
– Uniform 64 KByte overlay blocks for
SST49LF003A/004A/008A
– Top Boot Block protection
- 16 KByte for SST49LF002A
- 64 KByte for SST49LF003A/004A/008A
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance:100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
SST49LF002A: 4 seconds (typical)
SST49LF003A: 6 seconds (typical)
SST49LF004A: 8 seconds (typical)
SST49LF008A: 15 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Firmware Hub Interface (FWH) Mode for
in-system operation
– Parallel Programming (PP) Mode for fast
production programming
• Firmware Hub Hardware Interface Mode
– 5-signal communication interface supporting
byte Read and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Register for all blocks
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and
8-pin data I/O interface
– Supports fast In-System or PROM programming
for manufacturing
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST49LF00xA flash memory devices are designed
to be read-compatible with the Intel 82802 Firmware Hub
(FWH) device for PC-BIOS application. It provides pro-
tection for the storage and update of code and data in
addition to adding system design flexibility through five
general purpose inputs. Two interface modes are sup-
ported by the SST49LF00xA: Firmware Hub (FWH)
Interface Mode for In-System programming and Parallel
Programming (PP) Mode for fast factory programming of
PC-BIOS applications.
The SST49LF00xA flash memory devices are manufac-
tured with SST’s proprietary, high performance Super-
Flash Technology. The split-gate cell design and thick
oxide tunneling injector attain better reliability and manu-
facturability compared with alternate approaches. The
SST49LF00xA devices significantly improve performance
and reliability, while lowering power consumption. The
SST49LF00xA devices write (Program or Erase) with a
single 3.0-3.6V power supply. It uses less energy during
Erase and Program than alternative flash memory tech-
nologies. The total energy consumed is a function of the
applied voltage, current and time of application. Since for
©2001 Silicon Storage Technology, Inc.
S71161-06-000 9/01
504
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.







49LF002A pdf, 数据表
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Fiwrwmw.wDataaSrheeet4HU.ucomb
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
Advance Information
TABLE 6: BLOCK LOCKING REGISTER BITS
Reserved Bit [7..2]
000000
000000
000000
000000
Lock-Down Bit [1]
0
0
1
1
Write-Lock Bit [0]
0
1
0
1
Lock Status
Full Access
Write Locked (Default State at Power-Up)
Locked Open (Full Access Locked Down)
Write Locked Down
T6.3 504
Write Lock
The Write-Lock bit, bit 0, controls the lock state described in
Table 6. The default Write status of all blocks after power-
up is write locked. When bit 0 of the Block Locking register
is set, Program and Erase operations for the corresponding
block are prevented. Clearing the Write-Lock bit will unpro-
tect the block. The Write-Lock bit must be cleared prior to
starting a Program or Erase operation since it is sampled at
the beginning of the operation.
The Write-Lock bit functions in conjunction with the hard-
ware Write Lock pin TBL# for the top Boot Block. When
TBL# is low, it overrides the software locking scheme. The
top Boot Block Locking register does not indicate the state
of the TBL# pin.
The Write-Lock bit functions in conjunction with the hard-
ware WP# pin for blocks 0 to 6. When WP# is low, it over-
rides the software locking scheme. The Block Locking
register does not indicate the state of the WP# pin.
Lock Down
The Lock-Down bit, bit 1, controls the Block Locking regis-
ter as described in Table 6. When in the FWH interface
mode, the default Lock Down status of all blocks upon
power-up is not locked down. Once the Lock-Down bit is
set, any future attempted changes to that Block Locking
register will be ignored. The Lock-Down bit is only cleared
upon a device reset with RST# or INIT# or power down.
Current Lock Down status of a particular block can be
determined by reading the corresponding Lock-Down bit.
Once a block’s Lock-Down bit is set, the Write-Lock bits for
that block can no longer be modified, and the block is
locked down in its current state of write accessibility.
JEDEC ID Registers
The JEDEC ID registers for the boot device appear at
FFBC0000H and FFBC0001H in the 4 GByte system
memory map, and will appear elsewhere if the device is not
the boot device. Register is not available for read when the
device is in Erase/Program operation. Unused register
location will read as 00H. Refer to the relevant application
note for details. See Table 7 for the device ID code.
PARALLEL PROGRAMMING MODE
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. The data portion of the software com-
mand sequence is latched on the rising edge of WE#.
During the software command sequence the row address
is latched on the falling edge of R/C# and the column
address is latched on the rising edge of R/C#.
Read
The Read operation of the SST49LF00xA device is con-
trolled by OE#. OE# is the output control and is used to
gate data from the output pins. Refer to the Read cycle
timing diagram, Figure 14, for further details.
Reset
A VIL on RST# pin initiates a device reset.
Byte-Program Operation
The SST49LF00xA device is programmed on a byte-by-
byte basis. Before programming, one must ensure that the
sector, in which the byte which is being programmed exists,
is fully erased. The Byte-Program operation is initiated by
executing a four-byte command load sequence for Soft-
ware Data Protection with address (BA) and data in the last
byte sequence. During the Byte-Program operation, the
row address (A10-A0) is latched on the falling edge of R/C#
and the column Address (A21-A11) is latched on the rising
edge of R/C#. The data bus is latched in the rising edge of
WE#. The Program operation, once initiated, will be com-
pleted, within 20 µs. See Figure 15 for Program operation
timing diagram, Figure 18 for timing waveforms, and Figure
26 for its flowchart. During the Program operation, the only
valid reads are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform addi-
tional tasks. Any commands written during the internal Pro-
gram operation will be ignored.
©2001 Silicon Storage Technology, Inc.
8
S71161-06-000 9/01 504







49LF002A equivalent, schematic
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Fiwrwmw.wDataaSrheeet4HU.ucomb
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
Advance Information
NC
NC
NC
VSS (VSS)
IC (IC)
A10 (FGPI4)
R/C# (CLK)
VDD (VDD)
NC
RST# (RST#)
A9 (FGPI3)
A8 (FGPI2)
A7 (FGPI1)
A6 (FGPI0)
A5 (WP#)
A4 (TBL#)
1
2
3
4
5
6 Standard Pinout
7
8 Top View
9
10 Die Up
11
12
13
14
15
16
( ) Designates FWH Mode
FIGURE 7: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)
32 OE# (INIT#)
31 WE# (FWH4)
30 VDD (VDD)
29 DQ7 (RES)
28 DQ6 (RES)
27 DQ5 (RES)
26 DQ4 (RES)
25 DQ3 (FWH3)
24 VSS (VSS)
23 DQ2 (FWH2)
22 DQ1 (FWH1)
21 DQ0 (FWH0)
20 A0 (ID0)
19 A1 (ID1)
18 A2 (ID2)
17 A3 (ID3)
504 ILL F01.4
A7(FGPI1)
A6 (FGPI0)
A5 (WP#)
A4 (TBL#)
A3 (ID3)
A2 (ID2)
A1 (ID1)
A0 (ID0)
DQ0 (FWH0)
4 3 2 1 32 31 30
5 29
6 28
7 27
8 32-lead PLCC 26
9 25
10
Top View
24
11 23
12 22
13 21
14 15 16 17 18 19 20
IC (IC)
VSS (VSS)
NC
NC
VDD (VDD)
OE# (INIT#)
WE# (FWH4)
NC
DQ7 (RES)
( ) Designates FWH Mode
504 ILL F02.3
FIGURE 8: PIN ASSIGNMENTS FOR 32-LEAD PLCC
©2001 Silicon Storage Technology, Inc.
16
S71161-06-000 9/01 504










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