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零件编号 | H57V2582GTR | ||
描述 | 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O | ||
制造商 | Hynix Semiconductor | ||
LOGO | |||
1 Page
256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
www.DataSheet4U.com
256M (32Mx8bit) Hynix SDRAM
Memory
Memory Cell Array
- Organized as 4banks of 8,388,608 x 8
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Aug. 2009
1
111
Synchronous DRAM Memwowrwy.D2ata5S6heMet4bU.ictom
H57V2582GTR Series
ABSOLUTE MAXIMUM RATING
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD supply relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
TA
TSTG
VIN, VOUT
VDD, VDDQ
IOS
PD
Rating
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
Unit
oC
oC
V
V
mA
W
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VDD, VDDQ
VIH
VIL
Min Max
3.0 3.6
2.0 VDDQ + 0.3
-0.3 0.8
Unit
V
V
V
Note
1
1, 2
1, 3
Note: 1. All voltages are referenced to VSS = 0V.
2. VIH(Max) is acceptable VDDQ + 2V for a pulse width with <= 3ns of duration.
3. VIL(min) is acceptable -2.0V for a pulse width with <= 3ns of duration.
AC OPERATING TEST CONDITION (TA= 0 to 70oC, VDD=3.3±0.3V / VSS=0V)
Parameter
Symbol
Value
Unit
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
VIH / VIL
Vtrip
2.4 / 0.4
1.4
V
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
Voutref
CL
1.4
50
V
pF
Note: 1. See Next Page
Note
1
Rev 1.0 / Aug. 2009
8
111
Synchronous DRAM Memwowrwy.D2ata5S6heMet4bU.ictom
H57V2582GTR Series
CURRENT STATE TRUTH TABLE (Sheet 2 of 4)
Current
State
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Command
CS RAS CAS WE
BA0/
BA1
Amax-A0
HX X X
X
X
LL L L
OP CODE
LL L H
X
X
L L H L BA
X
LLHH
LH L L
LH L H
LHH H
HX X X
LL L L
LL L H
LLH L
LLHH
LH L L
LH L H
LHH H
HX X X
LL L L
LL L H
LLH L
LLHH
LH L L
LH L H
LHH H
HX X X
BA Row Add.
BA
Col Add.
A10
BA
Col Add.
A10
XX
XX
OP CODE
XX
BA X
BA Row Add.
BA Col Add. A10
BA Col Add. A10
XX
XX
OP CODE
XX
BA X
BA Row Add.
BA Col Add. A10
BA Col Add. A10
XX
XX
Description
Action
Device Deselect
Continue the Burst
Mode Register Set ILLEGAL
Auto or Self Refresh ILLEGAL
Precharge
Termination Burst: Start
the Precharge
Bank Activate
ILLEGAL
Write/WriteAP
Termination Burst: Start
Write(optional AP)
Read/ReadAP
Termination Burst: Start
Read(optional AP)
No Operation
Continue the Burst
Device Deselect
Continue the Burst
Mode Register Set ILLEGAL
Auto or Self Refresh ILLEGAL
Precharge
ILLEGAL
Bank Activate
ILLEGAL
Write/WriteAP
ILLEGAL
Read/ReadAP
ILLEGAL
No Operation
Continue the Burst
Device Deselect
Continue the Burst
Mode Register Set ILLEGAL
Auto or Self Refresh ILLEGAL
Precharge
ILLEGAL
Bank Activate
ILLEGAL
Write/WriteAP
ILLEGAL
Read/ReadAP
ILLEGAL
No Operation
Continue the Burst
Device Deselect
Continue the Burst
Notes
13
13
10
4
8
8,9
13
13
4,12
4,12
12
12
13
13
4,12
4,12
12
12
Rev 1.0 / Aug. 2009
16
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页数 | 22 页 | ||
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零件编号 | 描述 | 制造商 |
H57V2582GTR | 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O | Hynix Semiconductor |
H57V2582GTR-60C | 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O | Hynix Semiconductor |
H57V2582GTR-60I | 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O | Hynix Semiconductor |
H57V2582GTR-60J | 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O | Hynix Semiconductor |
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