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PDF ( 数据手册 , 数据表 ) 92RB25

零件编号 92RB25
描述 MSM92RB25
制造商 Oki Semiconductor
LOGO Oki Semiconductor LOGO 


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92RB25 数据手册, 描述, 功能
DATA SHEET
OKI
ASIC
www.DataSheet4U.com
PRODUCTS
MSM30R/32R/92R
0.5µm Sea Of Gates and
Customer Structured Arrays
August 2002







92RB25 pdf, 数据表
I MSM30R/32R/92R I ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
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DC Characteristics (VDD = 3.0 V ~ 3.6 V, VSS = 0 V, Tj = -40° C ~ +85° C)
Parameter
Symbol
Conditions
Rated Value
Min Typ [1]
High-level input voltage
TTL normal input
VIH
TTL 5V tolerant input
2.0
2.0
-
-
Low-level
input voltage
TTL normal input
VIL
TTL 5V tolerant input
-0.3
-0.3
-
-
TTL-level Schmitt Trigger
threshold voltage
(Normal buffer)
Vt+
Vt-
Vt
TTL normal input
Vt+ - Vt-
-
0.7
0.4
-
-
-
TTL-level Schmitt Trigger
threshold voltage
(5V tolerant buffer)
Vt+
TTL 5V tolerant input
Vt-
Vt Vt+ - Vt-
-
0.7
0.4
-
-
-
High-level output voltage
(Normal buffer)
High-level output voltage
(5V tolerant buffer)
VOH
IOH=-100 µA
IOH=-1,-2,-4,-6,-8,
-12,-24 mA
IOH=-100 µA
IOH=-1,-2,-4,-6,-8,
-12 mA
VDD-0.2
2.4
VDD-0.2
2.4
-
-
-
-
Low-level output voltage
(Normal buffer)
Low-level output voltage
(5V tolerant buffer)
VOL
IOL=100 µA
IOL=1,2,4,6,8,12,24
mA
IOL=100 µA
IOL=1,2,4,6,8,12 mA
-
-
-
-
-
-
-
-
Max
VDD+0.3
5.5
0.8
0.8
2.0
-
-
2.0
-
-
-
-
-
-
0.2
0.4
0.2
0.4
Unit
V
6 Oki Semiconductor







92RB25 equivalent, schematic
I MSM30R/32R/92R I ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
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Automatic Test Pattern Generation
Oki’s 0.5µm ASIC technologies support Automatic Test Pattern Generation (ATPG) using full scan-path
design techniques, including the following:
• Increases fault coverage 95%
• Uses Synopsys Test Compiler
• Automatically inserts scan structures
• Connects scan chains
• Traces and reports scan chains
• Checks for rule violations
• Generates complete fault reports
• Allows multiple scan chains
• Supports vector compaction
ATPG methodology is described in detail in Oki’s 0.5µm Scan Path Application Note.
Scan Data In
Scan Select
FD1AS
DQ
C
SD
SS QN
Combinational Logic
AB
FD1AS
DQ
C
SD
SS QN
Scan Data Out
Figure 13. Full Scan Path Configuration
Floorplanning Design Flow
Oki’s floorplanner can be classified as both a front-end floorplanner and a back-end floorplanner. During
front-end floorplanning, logic designers use the floorplanner to generate two files: a capacitance file for
pre-layout simulation, and a floorplanner interface file for layout.
During back-end floorplanning, the layout engineer transfers the floorplanner interface file to Oki’s pro-
prietary layout software, code-named Pegasus. The floorplanner interface file contains information about
the placement of blocks and groups of blocks. The back-end floorplanner is automated and is transparent
to logic designers.
Figure 14 shows a diagram of front-end floorplanning. Figure 15 shows a diagram of back-end floorplan-
ning.
14 Oki Semiconductor










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