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PDF ( 数据手册 , 数据表 ) N64S830HA

零件编号 N64S830HA
描述 64 kb Low Power Serial SRAMs
制造商 ON Semiconductor
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N64S830HA 数据手册, 描述, 功能
N64S830HA
64 kb Low Power Serial
SRAMs
8 k x 8 Bit Organization
Introduction
The ON Semiconductor serial SRAM family includes several
integrated memory devices including this 64 k serially accessed Static
Random Access Memory, internally organized as 8 k words by 8 bits.
The devices are designed and fabricated using ON Semiconductor’s
advanced CMOS technology to provide both highspeed performance
and low power. The devices operate with a single chip select (CS)
input and use a simple Serial Peripheral Interface (SPI) serial bus. A
single data in and data out line is used along with a clock to access data
within the devices. The N64S830HA devices include a HOLD pin that
allows communication to the device to be paused. While paused, input
transitions will be ignored. The devices can operate over a wide
temperature range of 40°C to +85°C and can be available in several
standard package offerings.
Features
Power Supply Range: 2.5 to 3.6 V
Very Low Standby Current: As low as 1 mA
Very Low Operating Current: As low as 3 mA
Simple Memory Control:
Single chip select (CS)
Serial input (SI) and serial output (SO)
Flexible Operating Modes:
Word read and write
Page mode (32 word page)
Burst mode (full array)
Organization: 8 k x 8 bit
Self Timed Write Cycles
Builtin Write Protection (CS High)
HOLD Pin for Pausing Communication
High Reliability: Unlimited write cycles
Green SOIC and TSSOP
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
MARKING
DIAGRAMS
TSSOP8
T SUFFIX
CASE 948AL
B125
XXXXYZZ
SOIC8
S SUFFIX
CASE 751BD
B115
XXXXYZZ
XXXX
Y
ZZ
= Date Code
= Assembly Code
= Lot Traceability
ORDERING INFORMATION
Device
N64S830HAS22I
N64S830HAT22I
N64S830HAS22IT
N64S830HAT22IT
Package
SOIC8
(PbFree)
TSSOP8
(PbFree)
SOIC8
(PbFree)
TSSOP8
(PbFree)
Shipping
100 Units / Tube
100 Units / Tube
3000 / Tape &
Reel
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
June, 2012 Rev. 12
1
Publication Order Number:
N64S830HA/D







N64S830HA pdf, 数据表
N64S830HA
SI
16bit address
Page address (X)
Word address (Y)
SO
Data Words: sequential, at the end of the page the
address wraps back to the beginning of the page
Page X
Word Y
Page X Page X
Word Y+1 Word Y+2
Page X
Word 31
Figure 8. Page READ Sequence
Page X
Word 0
Page X
Word 1
SI
16bit address
Page address (X)
Word address (Y)
SO
Page X
Word Y
Data Words: sequential, at the end of the page the address wraps to the beginning
of the page and continues incrementing up to the starting word address. At that
time, the address increments to the next page and the burst continues.
... ...
Page X
Word Y+1
Page X Page X
Word 31 Word 0
Page X
Word 1
Page X Page X+1 Page X+1
Word Y1 Word Y Word Y+1
Figure 9. Burst READ Sequence
WRITE Operations
The serial SRAM WRITE is selected by enabling CS low.
First, the 8bit WRITE instruction is transmitted to the
device followed by the 16bit address with the 3 MSBs
being don’t care. After the WRITE instruction and addresses
are sent, the data to be stored in memory is shifted in on the
SI pin.
If operating in page mode, after the initial word of data is
shifted in, additional data words can be written as long as the
address requested is sequential on the same page. Simply
write the data on SI pin and continue to provide clock pulses.
The internal address pointer is automatically incremented to
the next higher address on the page after each word of data
is written in. This can be continued for the entire page length
of 32 words long. At the end of the page, the addresses
pointer will be wrapped to the 0 word address within the
page and the operation can be continuously looped over the
32 words of the same page. The new data will replace data
already stored in the memory locations.
If operating in burst mode, after the initial word of data is
shifted in, additional data words can be written to the next
sequential memory locations by continuing to provide clock
pulses. The internal address pointer is automatically
incremented to the next higher address after each word of
data is read out. This can be continued for the entire array
and when the highest address is reached (1FFFh), the
address counter wraps to the address 0000h. This allows the
burst write cycle to be continued indefinitely. Again, the new
data will replace data already stored in the memory
locations.
All WRITE operations are terminated by pulling CS high.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11
21 22 23 24 25 26 27 28 29 30 31
Instruction
16bit address
Data In
SI 0 0 0 0 0 0 1 0 15 14 13 12 ... 2 1 0 7 6 5 4 3 2 1 0
SO HighZ
Figure 10. Word WRITE Sequence
http://onsemi.com
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