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PDF ( 数据手册 , 数据表 ) 71M6534H

零件编号 71M6534H
描述 Energy Meter IC
制造商 TERIDIAN Semiconductor
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71M6534H 数据手册, 描述, 功能
Simplifying System IntegrationTM
GENERAL DESCRIPTION
The 71M6533 and 71M6534 are Teridian’s 3rd-generation poly-
phase metering SOCs with a 10MHz 8051-compatible MPU
core, low-power RTC, FLASH and LCD driver. Teridian’s pa-
tented Single Converter Technology® with a 22-bit delta-sigma
ADC, seven analog inputs, digital temperature compensation,
precision voltage reference and a 32-bit computation engine
(CE) supports a wide range of metering applications with very
few external components.
The 71M6533 and 71M6534 add several new features to Teri-
dian’s flagship 71M6513 poly-phase meters including an SPI in-
terface, advanced power management with <1 µA sleep cur-
rent, 4 KB shared RAM and 128 KB (71M6533/H, 71M6534) or
256 KB (71M6534H) Flash which may be programmed in the
field with new code and/or data during meter operation. Higher
processing and sampling rates and larger memory offer a po-
werful metering platform for commercial and industrial meters
with up to class 0.2 accuracy.
A complete array of ICE and development tools, programming
libraries and reference designs enable rapid development and
certification of meters that meet all ANSI & IEC electricity meter-
ing standards worldwide.
LIVE
NEUT
LIVE
CT/ COIL
LIVE
AMR
IR
POWER
FAULT
LOAD
NEUTRAL
POWER SUPPLY
CONVERTER
IA
VA
IB
VB
IC
VC
ID
V3P3A V3P3SYS GNDA GNDD
TERIDIAN
71M6533
71M6534
PWR MODE
CONTROL
WAKE-up
REGULATOR
VBAT
V2P5
TEMP
SENSOR
LCD DRIVER
DIO ,PULSE
VREF
SERIAL PORTS
TX
RX
RAM
COMPUTE
ENGINE
COM0..3
SEG
SEG/ DIO
RX
MOD TX
COMPARATOR
V1
V2*
FLASH
MPU
RTC
TIMERS
ICE
DIO
OSC/ PLL
XIN
XOUT
* 71M6534 only
9/24/2008
BATTERY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
www.DataSheet4U.com
71M6533/H and 71M6534/H
Energy Meter IC
DATA SHEET
November 2009
FEATURES
Accuracy < 0.1% over 2000:1 range
Exceeds IEC62053 / ANSI C12.20 standards
Seven sensor inputs with neutral current
measurement
Low-jitter Wh and VARh plus two additional
pulse test outputs (4 total, 10 kHz maximum)
with pulse count
Four-quadrant metering
Phase sequencing
Line frequency count for RTC
Digital temperature compensation
Independent 32-bit compute engine
46-64 Hz line frequency range with same
calibration. Phase compensation ( 7 )
Three battery back-up modes with wake-up
on timer or push-button:
Brownout mode (82 µA typ., 71M6533)
LCD mode (21 µA typ., DAC active)
Sleep mode (0.7 µA typ.)
Energy display during mains power failure
39 mW typical consumption @ 3.3 V, MPU
clock frequency 614 kHz
8-bit MPU (80515), 1 clock cycle per in-
struction, 10 MHz maximum, with integrated
ICE for debug
LCD driver with 4 common segment drivers:
Up to 228 (71M6533) or 300 (71M6534)
pixels
4 dedicated plus 35 (71M6533) or
48 (71M6534) multi-function DIO pins
RTC for TOU functions with clock-rate adjust
register
Hardware watchdog timer, power fail monitor
I2C/Microwire EEPROM Interface
High-speed slave SPI interface to data RAM
Two UARTs for IR and AMR, IR driver with
modulation
Flash memory with security and in-system
program update:
128 KB (71M6533/H, 71M6534)
256 KB (71M6534H)
4 KB RAM
Industrial temperature range
100-pin (71M6533/H) or 120-pin
(71M6534/H) lead free LQFP package
v1.1 © 2007-2009 TERIDIAN Semiconductor Corporation 1







71M6534H pdf, 数据表
71M6533/71M6534 Data Sheet
FDS_653w3w_w6.D5a3ta4S_he0e0t44U.com
VREF
GNDA GNDD V3P3A V3P3SYS
IAP
IAN
VA
IBP
IBN
VB
ICP
ICN
VC
IDP
IDN
XIN
XOUT
TEST
RX
TX
PB
MUXP
VBAT
EQU
MUX_AL
MUX_DIV
TEMP
2.5V_NV
OSC
(32KHz)
ADC
CONVERTER
VBIAS
VADC
VREF
VREF_CAL
VREF_DIS
VBIAS
FIR
FIR_LEN 22
VB_REF
ADC_E
VDDREFZ
VREF
CE
PLS_INV
RTM
PLS_INTERVAL
PLS_MAXWIDTH
CE_LCTN
EQU
RPULSE
PRE_SAMPS WPULSE
SUM_CYCLES
RTM_0...3
XPULSE
RTM_E
CE_E
YPULSE
to TMUX
VOLT
REG
LCD_ONLY
SLEEP
CE_PROG
16
CE_DATA
32
2.5V to logic
2.5V_NV
MCK
RTCLK (32KHz) PLL
MPU_DIV
CKOUT_E
CK_CE
CK_MPU
FLASH
128KB
XRAM
4kB
DIO_PV
DIO_PW
DIO_PX
DIO_PY
RTCA_ADJ
2.5V_NV
TEST
MODE
RTC
RST_SUBSEC
QREG,PREG
RTC_DAY
RTC_HR RTC_DATE
RTC_MIN RTC_MO
RTC_SEC RTC_YR
MPU
8
3
CKTEST CKOUT_E
MULTI- 4
PURPOSE 5
I/O
3
COM0..3
LCD DISPLAY
DRIVER
4
LCD_DAC
LCD_MODE
LCD_CLK
LCD_E
LCD_BLKMAP
LCD_SEG
LCD_Y
Segments
4
4
2
5
UART1
PB
XRAM BUS
8
DIGITAL I/O
DIO_DIR
DIO_R
DIO
SPI SLAVE
PCMD
DIO_1..24
24
PCSZ
PCLK
PSI
PSO
SPE
9
2
EEPROM I/F
EEDATA
EECTRL
SDATA
SCLK DIO_EEX
VBIAS
UART2/OPTICAL
OPT_RXDIS
OPT_RXINV
OPT_TXE
OPT_TXINV
OPT_TXMOD
OPT_FDC
OPT_TX
OPT_RX
OPT_TXE
4
7
V2* + V2_OK*
-
V1 POWER FAULT FAULTZ
IRAM BUS IRAM
256B
8
NV RAM
GP0-GP7
2.5V_NV
EMULATOR
ICE_E
E_RXTX
E_TCLK
E_RSTZ
ICE_E
TEST
MUX
TMUX[4:0]
3
V3P3D
VBAT
V2P5
DIO56...DIO58
DIO52/SEG72*...DIO55/SEG75*
DIO47/SEG67...DIO51/SEG71
DIO46/SEG66*
DIO43/SEG63...DIO45/SEG65
DIO42/SEG62*
COM3..0
DIO41/SEG61
DIO36/SEG56*...DIO39/SEG59*
DIO29/SEG49...DIO30/SEG50
DIO28/SEG48*
DIO23/SEG43...DIO27/SEG47
DIO22/SEG42*
DIO13/SEG33...DIO21/SEG41
DIO12/SEG32*
DIO10/SEG30...DIO11/SEG31
DIO9/SEG29/YPULSE
DIO8/SEG28/XPULSE
DIO7/SEG27/RPULSE
DIO6/SEG26/WPULSE
DIO5/SEG25/SDATA
DIO4/SEG24/SDCK
DIO3
DIO2/OPT_TX
DIO1/OPT_RX
SEG20...SEG23
SEG12 ...SEG18
SEG11/E_RST
SEG10/E_TCLK
SEG9/E_RXTX
SEG8
SEG7/MUX_SYNC
SEG6/PSDI
SEG5/PCSZ
SEG4/PSDO
SEG3/PCLK
SEG0...SEG2
TMUXOUT
* 71M6534/6534H only
RESET
ICE_E
3/10/2009
Figure 1: IC Functional Block Diagram
8
© 2007-2009 TERIDIAN Semiconductor Corporation
v1.1







71M6534H equivalent, schematic
71M6533/71M6534 Data Sheet
FDS_653w3w_w6.D5a3ta4S_he0e0t44U.com
1.2.12 Pulse Generators
The 71M6533 and 71M6534 provide four pulse generators, RPULSE, WPULSE, XPULSE and YPULSE,
as well as hardware support for the RPULSE and WPULSE pulse generators. The pulse generators can
be used to output CE status indicators, SAG for example, to DIO pins.
The polarity of the pulses may be inverted with PLS_INV. When this bit is set, the pulses are active high,
rather than the more usual active low. PLS_INV inverts all the pulse outputs.
XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse outputs. Pins DIO8
and DIO9 are used for these pulses. Generally, the XPULSE and YPULSE outputs are updated once on
each pass of the CE code, resulting in a pulse frequency up to a maximum of 1260Hz (assuming a MUX
frame is 13 CK32 cycles).
Standard CE code permits the selection of either an energy indication or signaling of a sag event for the
YPULSE output. See Section 4.3 CE Interface Description for details.
RPULSE and WPULSE
During each CE code pass, the hardware stores exported WPULSE AND RPULSE sign bits in an 8-bit FIFO
and outputs them at a specified interval. This permits the CE code to calculate the RPULSE and WPULSE
outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX frame. The
FIFO is reset at the beginning of each MUX frame. PLS_INTERVAL[7:0] controls the delay to the first pulse
update and the interval between subsequent updates. The LSB of PLS_INTERVAL[7:0] is equivalent to 4
CK_FIR cycles. If zero, the FIFO is deactivated and the pulse outputs are updated immediately. Thus,
NINTERVAL is 4*PLS_INTERVAL.
Since the FIFO resets at the beginning of each MUX frame, the user must specify PLS_INTERVAL so that
all of the pulse updates are output before the MUX frame completes. For instance, if the CE code outputs
6 updates per MUX interval, and if the MUX interval is 1950 cycles long, the ideal value for the interval is
1950/6/4 = 81.25. If PLS_INTERVAL = 82, the fifth output will occur too late and be lost. In this case, the
proper value for PLS_INTERVAL is 81.
Hardware also provides a maximum pulse width feature: PLS_MAXWIDTH[7:0] selects a maximum nega-
tive pulse width to be Nmax updates according to the formula: Nmax = (2*PLS_MAXWIDTH+1). If
PLS_MAXWIDTH=255, no width checking is performed.
The WPULSE and RPULSE pulse generator outputs are available on DIO6 and DIO7, respectively. They
can also be output on OPT_TX (see OPT_TXE[1:0] for details).
1.2.13 Data RAM (XRAM)
In the 71M6533/71M6534, the CE and MPU use a single general-purpose Data RAM (also referred to as
XRAM). The Data RAM is 1024 32-bit words, shared between the CE and the MPU using a time-multi-
plex method. This reduces MPU wait states when accessing CE data. When the MPU and CE are clock-
ing at maximum frequency (10 MHz), the DRAM will make up to four accesses during each 100 ns inter-
val. These consist of two MPU accesses, one CE access and one SPI access.
The Data RAM is 32 bits wide and uses an external multiplexer so as to appear byte-wide to the MPU.
The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that
requires two Data RAM accesses. The second access is guaranteed to be available because the MPU
cannot access the XRAM on two consecutive instructions unless it is using the same address.
In addition to the reduction of wait states, this arrangement permits the MPU to easily use unneeded CE data
memory. Likewise, the amount of memory the CE uses is not limited by the size of a dedicated CE data RAM.
16
© 2007-2009 TERIDIAN Semiconductor Corporation
v1.1










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