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PDF ( 数据手册 , 数据表 ) 71M6521BE

零件编号 71M6521BE
描述 Energy Meter IC
制造商 TERIDIAN Semiconductor
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71M6521BE 数据手册, 描述, 功能
GENERAL DESCRIPTION
The TERIDIAN 71M6521BE is a highly integrated SOC with an MPU core,
FLASH and LCD driver. TERIDIAN’s patented Single Converter Technol-
ogywith a 22-bit delta-sigma ADC, four analog inputs, digital temperature
compensation, precision voltage reference, battery voltage monitor, and 32-
bit computation engine (CE) supports a wide range of residential metering
applications with very few low-cost external components. A 32kHz crystal
time-base for the entire system further reduces system cost. The IC
supports 2-wire single-phase residential metering along with tamper-
detection mechanisms.
Maximum design flexibility is provided by multiple UARTs, I2C, μWire, up to
14 DIO pins and in-system programmable FLASH memory, which can be
updated with data or application code in operation.
A complete array of ICE and development tools, programming libraries and
reference designs enable rapid development and certification of AMR and
Prepay meters that comply with worldwide electricity metering standards.
A
NEUT
B
CT/SHUNT
LOAD
LOAD
POWER SUPPLY
AMR
RX/DIO1
IR TX/DIO2
POWER
FAULT
32 kHz
CONVERTER
IA
VA
IB
VB
V3.3A
V3.3
SYS
TERIDIAN
71M6521BE
GNDA GNDD
PWR MODE
CONTROL
WAKE-UP
REGULATOR
VBAT
V2.5
VOLTAGE REF
VREF
VBIAS
SERIAL PORTS
TX
RX
SENSE
DRIVE/MOD
COMPARATOR
V1
OSC/PLL
XIN
XOUT
TEMP
SENSOR
RAM
FLASH
COMPUTE
ENGINE
MPU
TIMERS
ICE
DIO, PULSE
COM0..3
SEG0..18
SEG 24..31/
DIO 4..11
SEG 34..37/
DIO 14..17
SEG 32,33,
38
ICE_E
11/14/2007
BATTERY
3.3V LCD
888888.88
I2C or µWire
EEPROM
TEST PULSE
V3P3D
GNDD
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71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
FEATURES
< 0.4% Wh accuracy over 2000:1 current range
and over temperature
Exceeds IEC62053 / ANSI C12.20 standards
Voltage reference < 40ppm/°C
Four sensor inputs—VDD referenced
Low jitter Wh test output (10kHz maximum)
Pulse count for Wh pulse output
Tamper detection: Neutral current with CT or
shunt
Line frequency count for time keeping
Digital temperature compensation
Sag detection for phase A and B
Independent 32-bit compute engine
46-64Hz line frequency range with same
calibration
Phase compensation (±7°)
Battery monitor
Three battery modes w/ wake-up on push-button
or timer:
Brownout mode (48µA)
LCD mode (5.7µA)
Sleep mode (2.9µA)
Energy display on main power failure
Wake-up with push-button
22-bit delta-sigma ADC
8-bit MPU (80515), 1 clock cycle per instruction
w/ integrated ICE for MPU debug
Hardware watchdog timer, power fail monitor
LCD driver (up to 140 pixels)
Up to 14 general purpose I/O pins
32kHz time base
8KB FLASH with security
2KB MPU XRAM
Two UARTs for IR and AMR
Digital I/O pins compatible with 5V inputs
64-pin LQFP
Lead Free package
V1.0
© 2005-2008 TERIDIAN Semiconductor Corporation
Page: 1 of 97







71M6521BE pdf, 数据表
www.DataSheet4U.com
71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
VREF
V3P3A GNDA V3P3SYS
IA
VA
IB
VB
X4MHZ
XIN
XOUT
CKTEST/
SEG19
TEST
MUX
VBIAS
TEMP
MUX
MUX
CTRL
EQU
MUX_ALT
CHOP_E
MUX_DIV
VREF
VREF_CAL
VREF_DIS
CROSS
CK32
VBIAS
ΔΣ ADC
CONVERTER
V3P3A
-
+
ADC_E
VREF
FIR
FIR_LEN
OSC
(32KHz)
32KHz
CKOUT_E
4.9MHz
CK_GEN
CK_2X
MCK
PLL
CK32
32KHz
DIV
ADC
CKOUT_E
CKADC
4.9MHz
ECK_DIS
MPU_DIV
MUX_SYNC STRT
TEST
MODE
CKCE
<4.9MHz
CE
32 bit Compute
Engine
WPULSE
VARPULSE
RTM
DATA
00-7F
CE
CONTROL
PROG
000-1FF
CKFIR
4.9MHz
CE RAM
(0.5KB)
MUX
MEMORY SHARE
1000-11FF
PLS_INV
PLS_INTERVAL
PLS_MAXWIDTH
CE_LCTN
EQU
PRE_SAMPS
SUM_CYCLES
RTM_0..3
RTM_E
CE_E
EEPROM
INTERFACE
WPULSE
VARPULSE
VOLT
REG
LCD_ONLY
SLEEP
2.5V to logic
V3P3D
LCD_GEN VLC2
VLC1
LCD_MODE
LCD_E
VLC0
LCD DISPLAY
DRIVER
LCD_NUM
LCD_MODE
LCD_CLK
LCD_E
LCD_BLKMAP
LCD_SEG
LCD_Y
DIGITAL I/O
DIO_EEX
DIO_PV/PW
DIO_DIR
DIO_R
LCD_NUM
DIO
SEG32,33
SEG19,38
DIO1,2
V3P3D
VBAT
GNDD
V2P5
COM0..3
SEG0..18
SEG24/DIO4 ..
SEG31/DIO11
SEG34/DIO14 ..
SEG37/DIO17
PB
RX
TX
OPT_RX/
DIO1
OPT_TX/
DIO2/
WPULSE/
VARPULSE
V1
UART
OPTICAL
CKMPU
<4.9MHz
MPU
(80515)
SDCK
SDOUT
SDIN
DATA
0000-FFFF
2000-20FF
CONFIGURATION
CONFIG
PARAMETERS
(I/O RAM)
0000-07FF
MPU XRAM
(2KB)
OPT_RXDIS
OPT_RXINV
OPT_TXE
OPT_TXINV
OPT_TXMOD
OPT_FDC
VBIAS
PROG
0000-1FFF
MEMORY
SHARE
CE_LCTN
0000-
1FFF
FLASH
8KB
FLSH66ZT
POWER FAULT
COMP_STAT
WAKE
FAULTZ
MPU_RSTZ
EMULATOR
PORT
E_RXTX
E_TCLK
E_RST (Open Drain)
TEST
MUX
TMUX[4:0]
RESET
E_RXTX/SEG38
E_TCLK/SEG33
E_RST/SEG32
ICE_E
February 2, 2007
TMUXOUT
Figure 1: IC Functional Block Diagram
Page: 8 of 97
© 2005-2008 TERIDIAN Semiconductor Corporation
V1.0







71M6521BE equivalent, schematic
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71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
80515 MPU Core
The 71M6521BE includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a
5MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and im-
plements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, there-
fore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average) improvement
(in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations,
AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register
MPU_DIV[2:0].
Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are
available for the MPU as part of TERIDIAN’s standard library. A standard ANSI “C” 80515-application programming interface
library is available to help reduce design cycle.
Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program
memory (Flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, and I/O RAM, and internal data
memory (Internal RAM). Table 3 shows the memory map.
Address
(hex)
0000-1FFF
on 1K
boundary
0000-07FF
1000-11FF
2000-20FF
Memory
Technology
Flash Memory
Flash Memory
Static RAM
Static RAM
Static RAM
Memory Type
Typical Usage
Non-volatile
Non-volatile
Volatile
Volatile
Volatile
MPU Program and non-
volatile data
CE program
MPU data XRAM,
CE data
Configuration RAM
I/O RAM
Table 3: Memory Map
Wait States
(at 5MHz)
0
0
0
6
0
Memory Size
(bytes)
8K
2K
2K
512
256
Internal and External Data Memory: Both internal and external data memory are physically located on the 71M6521BE IC.
“External” data memory is only external to the 80515 MPU core.
Program Memory: The 80515 can theoretically address up to 64KB of program memory space from 0x0000 to 0xFFFF.
Program memory is read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and
interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003.
External Data Memory: While the 80515 is capable of addressing up to 64KB of external data memory in the space from
0x0000 to 0xFFFF, only the memory ranges shown in Error! Reference source not found. contain physical memory. The
80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU
reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8
bytes for the MOVX A,@Ri instruction).
Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low order bits
of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very slow
external RAM or external peripherals.
Page: 16 of 97
© 2005-2008 TERIDIAN Semiconductor Corporation
V1.0










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