DataSheet8.cn


PDF ( 数据手册 , 数据表 ) TSA1002

零件编号 TSA1002
描述 50mW A/D CONVERTER
制造商 STMicroelectronics
LOGO STMicroelectronics LOGO 


1 Page

No Preview Available !

TSA1002 数据手册, 描述, 功能
www.DataSheet4U.com
TSA1002
10-BIT, 50MSPS, 50mW A/D CONVERTER
NOT FOR NEW DESIGN
P 10-bit A/D converter in deep submicron
ORDER CODE
CMOS technology
P Single supply voltage: 2.5V
P Input range: 2Vpp differential
P 50Msps sampling frequency
P Ultra low power consumption: 50mW @
50Msps
P ENOB=9.6 @ 40Msps, Fin=24MHz
P SFDR typically up to 72dB @ 50Msps,
Fin=5MHz
Part Number
Temperature
Range
TSA1002CF
TSA1002CFT
TSA1002IF
TSA1002IFT
EVAL1002/AA
0 C to +70 C
0 C to +70 C
-40 C to +85 C
-40 C to +85 C
Package Conditioning Marking
TQFP48
Tray
TQFP48 Tape & Reel
TQFP48
Tray
TQFP48 Tape & Reel
Evaluation board
SA1002C
SA1002C
SA1002I
SA1002I
P Built-in reference voltage with external bias
capability
)P Pinout compatibility with TSA0801, TSA1001
t(sand TSA1201
cDESCRIPTION
duThe TSA1002 is a 10-bit, 50Msps sampling
rofrequency Analog to Digital converter using a
CMOS technology combining high performances
Pand very low power consumption.
teThe TSA1002 is based on a pipeline structure and
ledigital error correction to provide excellent static
olinearity and guarantee 9.6 effective bits at
sFs=40Msps, and Fin=24MHz.
bA voltage reference is integrated in the circuit to
Osimplify the design and minimize external
-components. It is nevertheless possible to use the
)circuit with an external reference.
t(sEspecially designed for high speed, low power
capplications, the TSA1002 only dissipates 50mW
uat 50Msps. A tri-state capability, available on the
doutput buffers, enables to address several slave
roADCs by a unique master.
PThe output data can be coded into two different
formats. A Data Ready signal is raised as the data
teis valid on the output and can be used for
lesynchronization purposes.
oThe TSA1002 is available in commercial (0 to
s+70 C) and extended (-40 to +85 C) temperature
Obrange, in a small 48 pins TQFP package.
PIN CONNECTIONS (top view)
index
corner
48 47 46 45 44 43 42 41 40 39 38 37
IPOL
VREFP
VREFM
AGND
VIN
1
2
3
4
5
AGND
VINB
AGND
6
7
8
INCM 9
AGND 10
AVCC 11
AVCC 12
TSA1002
36 NC
35 NC
34 NC
33 D0 (LSB)
32 D1
31 D2
30 D3
29 D4
28 D5
27 D6
26 D7
25 D8
13 14 15 16 17 18 19 20 21 22 23 24
PACKAGE
7 x 7 mm TQFP48
APPLICATIONS
P Medical imaging and ultrasound
P Portable instrumentation
P Cable Modem Receivers
P High resolution fax and scanners
P High speed DSP interface
April 2004
1/20







TSA1002 pdf, 数据表
TSA1002
www.DataSheet4U.com
DEFINITIONS OF SPECIFIED PARAMETERS
Signal to Noise Ratio (SNR)
STATIC PARAMETERS
The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
Static measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 40Msps, which is high enough to fully
components in the Nyquist band (fs/2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
characterize the test frequency response. The
input level is +1dBFS to saturate the signal.
Signal to Noise and Distortion Ratio (SINAD)
Similar ratio as for SNR but including the harmonic
Differential Non Linearity (DNL)
The average deviation of any output code width
from the ideal code width of 1 LSB.
distortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
Integral Non linearity (INL)
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
An ideal converter presents a transfer function as has an A0 amplitude, the SINAD expression
being the straight line from the starting code to the
ending code. The INL is the deviation for each
)transition from this ideal curve.
ct(sDYNAMIC PARAMETERS
duDynamic measurements are performed by
rospectral analysis, applied to an input sine wave of
various frequencies and sampled at 40Msps.
te PThe input level is -1dBFS to measure the linear
behavior of the converter. All the parameters are
legiven without correction for the full scale ampli-
otude performance except the calculated ENOB
sparameter.
ObSpurious Free Dynamic Range (SFDR)
) -The ratio between the power of the worst spurious
t(ssignal (not always an harmonic) and the amplitude
of fundamental tone (signal power) over the full
cNyquist band. It is expressed in dBc.
roduTotal Harmonic Distortion (THD)
PThe ratio of the rms sum of the first five harmonic
tedistortion components to the rms value of the
Obsolefundamental line. It is expressed in dB.
becomes:
SINAD2Ao=SINADFull Scale+ 20 log (2A0/FS)
SINAD2Ao=6.02 × ENOB + 1.76 dB + 20 log (2A0/
FS)
The ENOB is expressed in bits.
Analog Input Bandwidth
The maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller input levels.
Effective Resolution Bandwidth (ERB)
The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
Pipeline delay
Delay between the initial sample of the analog
input and the availability of the corresponding
digital data output, on the output bus. Also called
data latency. It is expressed as a number of clock
cycles.
8/20







TSA1002 equivalent, schematic
www.DataSheet4U.com
TSA1002
Power consumption
The internal architecture of the TSA1002 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between IPOL and
the analog Ground pins. The figure 10 sums up
the relevant data.
The TSA1002 will combine highest performances
and lowest consumption at 50Msps when Rpol is
in the range of 12kto 20k.
At lower sampling frequency, this value of resistor
may be changed and the consumption will
decrease as well.
Figure 10 : Analog Current consumption vs. Fs
According value of Rpol polarization resistance
Distortion vs. Duty cycle
Fs=50MSPS; consumption optimized; Fin=1MHz
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
30
THD
SFDR
IccA
40 50 60
Duty Cycle (%)
70
60
50
40
30
20
10
70
60
)50
t(s40
c30
du20
ro10
te P0
le25
RPOL
ICCA
35 45 55 65
Fs (MHz)
20
18
16
14
12
10
8
6
4
2
0
75
bsoLinearity, distortion performance towards
OClock Duty Cycle variation
) -The TSA1002 has an outstanding behaviour
t(stowards clock duty cycle variation and it may be
calso reinforced with adjustment of analog current
uconsumption.
rodLinearity vs. Duty cycle
Fs=50MSPS; consumption optimized; Fin=1MHz
te P80 10
le ENOB
70 9
so60
SNR
8
b 50 SINAD
O7
Linearity vs. Duty cycle
Fs=50MSPS; Icca=20mA; Fin=10MHz
80
75
70
65
60
55
50
45
40
35
30
40
ENOB
SNR
SINAD
45 50 55
Duty Cycle (%)
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
60
Distortion vs. Duty cycle
Fs=50MSPS; Icca=20mA; Fin=10MHz
0
-10
-20
-30
-40
-50
40 THD
IccA
6 -60
30
20
-70
5
-80
SFDR
10 4 -90
03
30 40 50 60 70
Duty Cycle (%)
-100
40
45 50 55
Duty Cycle (%)
60
16/20










页数 20 页
下载[ TSA1002.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
TSA1001A/D CONVERTERST Microelectronics
ST Microelectronics
TSA100250mW A/D CONVERTERSTMicroelectronics
STMicroelectronics
TSA1005A/D CONVERTERST Microelectronics
ST Microelectronics

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap