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PDF ( 数据手册 , 数据表 ) W77E532A

零件编号 W77E532A
描述 8-BIT MICROCONTROLLER
制造商 Winbond
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W77E532A 数据手册, 描述, 功能
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W77E532/W77E532A DATA SHEET
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 2
2. FEATURES ................................................................................................................................. 2
3. PIN CONFIGURATIONS ............................................................................................................ 3
4. PIN DESCRIPTION..................................................................................................................... 4
5. FUNCTIONAL DESCRIPTION ................................................................................................... 6
6. MEMORY ORGANIZATION ....................................................................................................... 8
7. INSTRUCTION.......................................................................................................................... 32
8. INSTRUCTION TIMING ............................................................................................................ 33
9. POWER MANAGEMENT.......................................................................................................... 41
10. INTERRUPTS ........................................................................................................................... 46
11. PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 49
12. SERIAL PORT .......................................................................................................................... 58
13. TIMED ACCESS PROTECTION .............................................................................................. 65
14. H/W REBOOT MODE (BOOT FROM 4K BYTES OF LDFLASH ) ........................................... 67
15. IN-SYSTEM PROGRAMMING ................................................................................................. 68
15.1 The Loader Program Locates at LDFLASH Memory ................................................... 68
15.2 The Loader Program Locates at APFLASH Memory ................................................... 68
16. H/W WRITER MODE ................................................................................................................ 68
17. SECURITY BITS ....................................................................................................................... 69
18. ELECTRICAL CHARACTERISTICS......................................................................................... 70
18.1 Absolute Maximum Ratings .......................................................................................... 70
18.2 DC Characteristics........................................................................................................ 70
18.3 AC Characteristics ........................................................................................................ 71
18.3.1 AC Specification .......................................................................................................... 72
18.3.2 MOVX Characteristics Using Strech Memory Cycle .................................................... 73
18.3.3 Program Memory Read Cycle ..................................................................................... 74
18.3.4 Data Memory Read Cycle............................................................................................ 75
18.3.5 Data Memory Write Cycle............................................................................................ 75
19. TYPICAL APPLICATION CIRCUITS ........................................................................................ 76
19.1 Crystal connections ...................................................................................................... 76
19.2 Expanded External Data Memory and Oscillator ......................................................... 77
20. PACKAGE DIMENSIONS ......................................................................................................... 78
20.1 40-pin DIP ..................................................................................................................... 78
20.2 44-pin PLCC ................................................................................................................. 78
20.3 44-pin QFP.................................................................................................................... 79
21. APPLICATION NOTE ............................................................................................................... 80
22. REVISION HISTORY ................................................................................................................ 85
Publication Release Date: November 19, 2007
- 1 - Revision A9







W77E532A pdf, 数据表
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W77E532/W77E532A
6. MEMORY ORGANIZATION
The W77E532A separates the memory into two separate sections, the Program Memory and the Data
Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is
used to store data or for memory mapped devices.
Program Memory
The Program Memory on the standard 8052 can only be addressed to 64 Kbytes long. By invoking the
banking methodology, W77E532A can extend to two 64KB flash EPROM banks, APFLASH0 and
APFLASH1. There are on-chip ROM banks which can be used similarly to that of the 8052. All
instructions are fetched for execution from this memory area. The MOVC instruction can also access
this memory region. There is an auxiliary 4KB Flash EPROM bank (LDFLASH) resided user loader
program for In-System Programming (ISP). Both APFLASHs allow serial or parallel download
according to user loader program in LDFLASH.
Data Memory
The W77E532A can access up to 64Kbytes of external Data Memory. This memory region is
accessed by the MOVX instructions. Unlike the 8051 derivatives, the W77E532A contains on-chip 1K
bytes MOVX SRAM of Data Memory, which can only be accessed by MOVX instructions. These 1K
bytes of SRAM are between address 0000H and 03FFH. Access to the on-chip MOVX SRAM is
optional under software control. When enabled by software, any MOVX instruction that uses this area
will go to the on-chip RAM. MOVX addresses greater than 03FFH automatically go to external
memory through Port 0 and 2. When disabled, the 1KB memory area is transparent to the system
memory map. Any MOVX directed to the space between 0000H and FFFFH goes to the expanded
bus on Port 0 and 2. This is the default condition. In addition, the W77E532A has the standard 256
bytes of on-chip Scratchpad RAM. This can be accessed either by direct addressing or by indirect
addressing. There are also some Special Function Registers (SFRs), which can only be accessed by
direct addressing. Since the Scratchpad RAM is only 256 bytes, it can be used only when data
contents are small. In the event that larger data contents are present, two selections can be used.
One is on-chip MOVX SRAM , the other is the external Data Memory. The on-chip MOVX SRAM can
only be accessed by a MOVX instruction, the same as that for external Data Memory. However, the
on-chip RAM has the fastest access times.
FFh Indirect
Addressing
RAM
80h
7Fh Direct &
Indirect
Addressing
00h RAM
SFRs
Direct
Addressing
03FFh
0000h
1K Bytes
On-chip SRAM
64 K
Bytes
External
Data
Memory
FFFFh
64K Bytes
On-chip
Program
Memory
APROM0
64K Bytes
On-chip
Program
Memory
APROM1
0000h
Figure 1. Memory Map
4K Bytes
LDROM
0FFFh
Publication Release Date: November 19, 2007
- 8 - Revision A9







W77E532A equivalent, schematic
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W77E532/W77E532A
Port 1
Bit: 7 6 5 4 3 2 1 0
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
Mnemonic: P1
Address: 90h
P1.70: General purpose I/O port. Most instructions will read the port pins in case of a port read
access, however in case of read-modify-write instructions, the port latch is read. Some pins
also have alternate input or output functions. This alternate functions are described below:
P1.0 : T2 External I/O for Timer/Counter 2
P1.1 : T2EX Timer/Counter 2 Capture/Reload Trigger
P1.2 : RXD1 Serial Port 1 Receive
P1.3 : TXD1 Serial Port 1 Transmit
P1.4 : INT2 External Interrupt 2
P1.5 : INT3 External Interrupt 3
P1.6 : INT4 External Interrupt 4
P1.7 : INT5 External Interrupt 5
External Interrupt Flag
Bit: 7 6 5 4 3 2 1 0
IE5 IE4 IE3 IE2
-
-
-
-
Mnemonic: EXIF
Address: 91h
IE5: External Interrupt 5 flag. Set by hardware when a falling edge is detected on INT5 .
IE4: External Interrupt 4 flag. Set by hardware when a rising edge is detected on INT4.
IE3: External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT3 .
IE2: External Interrupt 2 flag. Set by hardware when a rising edge is detected on INT2.
Port 4 Control Register A
Bit: 7
P41M1
6
P41M0
5
P41C1
4
P41C0
3
P40M1
2
P40M0
1
P40C1
0
P40C0
Mnemonic: P4CONA
Address: 92h
Port 4 Control Register B
Bit: 7
P43M1
6
P43M0
5
P43C1
4
P43C0
3
P42M1
2
P42M0
1
P42C1
0
P42C0
Mnemonic: P4CONB
Address: 93h
- 16 -
Publication Release Date: November 19, 2007
Revision A9










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