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PDF ( 数据手册 , 数据表 ) H5DU2562GTR

零件编号 H5DU2562GTR
描述 (H5DU2562GTR / H5DU2582GTR) 256Mb DDR SDRAM
制造商 Hynix Semiconductor
LOGO Hynix Semiconductor LOGO 


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H5DU2562GTR 数据手册, 描述, 功能
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256Mb DDR SDRAM
H5DU2562GTR
H5DU2582GTR
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1 / Sep. 2009
1







H5DU2562GTR pdf, 数据表
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H5DU2562GTR
H5DU2582GTR
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1 CKEn
/CS
/RAS /CAS
/WE
ADDR A10/AP BA
Extended Mode Register Set1,2
H
X
L
L
L
L
OP code
Mode Register Set1,2
HXLLLL
OP code
Device Deselect1
No Operation1
HXXX
HX
L HHH
X
Bank Active1
H X L LHH
RA V
Read1
L
H X L H L H CA
V
Read with Autoprecharge1,3
H
Write1
L
H X L H L L CA
V
Write with Autoprecharge1,4
H
Precharge All Banks1,5
HX
H X LLHLX
Precharge selected Bank1
LV
Read Burst Stop1
H X LHHL
X
Auto Refresh1
H H L L LH
X
Entry
H
L
L
L
LH
Self Refresh1
Exit
L
H
HXXX
L HHH
X
HXXX
Precharge Power
Entry
H
L
L HHH
Down Mode1
Exit
L
H
HXXX
L HHH
X
HXXX
Active Power
Down Mode1
Entry
H
L
L
VVV
Exit L
H
X
X
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note:
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Precharge command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been
completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
*For more information about Truth Table, refer to “Device Operation” section in Hynix website.
Rev. 1.1 / Sep. 2009
8







H5DU2562GTR equivalent, schematic
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H5DU2562GTR
H5DU2582GTR
EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-
tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits
shown below. The Extended Mode Register is programmed via the Mode Register Set command (BA0=1 and BA1=0)
and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01
Operating Mode
0* DS DLL
BA0 MRS Type
0 MRS
1 EMRS
A0 DLL enable
0 Enable
1 Disable
A1
Output Driver
Impedance Control
0 Full Strength Driver
1 Half Strength Driver
An~A3
0
_
A2~A0
Valid
_
Operating Mode
Normal Operation
All other states reserved
* This part do not support/QFC function, A2 must be programmed to Zero.
Rev. 1.1 / Sep. 2009
16










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