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PDF ( 数据手册 , 数据表 ) TJA1043

零件编号 TJA1043
描述 High-speed CAN transceiver
制造商 NXP Semiconductors
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TJA1043 数据手册, 描述, 功能
TJA1043
High-speed CAN transceiver
Rev. 01 — 30 March 2010
www.DataSheet4U.com
Product data sheet
1. General description
The TJA1043 is a high-speed CAN transceiver that provides an interface between a
Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus.
The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in the
automotive industry, providing differential transmit and receive capability to (a
microcontroller with) a CAN protocol controller.
The TJA1043 is a step up from the TJA1041A high-speed CAN transceiver. It offers
improved ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Discharge (ESD)
performance, very low power consumption, and passive behavior when the supply voltage
is turned off. Advanced features include:
Low-power management controls the power supply throughout the node while
supporting local and remote wake-up with wake-up source recognition
Several protection and diagnostic functions including bus line short-circuit detection
and battery connection detection
Can be interfaced directly to microcontrollers with supply voltages from 3 V to 5 V
These features make the TJA1043 the ideal choice for high speed CAN networks
containing nodes that need to be available all times, even when the internal VIO and VCC
supplies are switched off.
2. Features and benefits
2.1 General
„ Fully ISO 11898-2 and ISO 11898-5 compliant
„ Suitable for 12 V and 24 V systems
„ Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)
„ VIO input allows for direct interfacing with 3 V and 5 V microcontrollers
„ SPLIT voltage output for stabilizing the recessive bus level
„ Listen-only mode for node diagnosis and failure containment
2.2 Low-power management
„ Very low current Standby and Sleep modes, with local and remote wake-up
„ Capability to power down the entire node while supporting local, remote and host
wake-up
„ Wake-up source recognition
„ Transceiver disengages from the bus (zero load) when VBAT absent
„ Functional behavior predictable under all supply conditions







TJA1043 pdf, 数据表
NXP Semiconductors
www.DataSheet4U.com
TJA1043
High-speed CAN transceiver
Table 4. Accessing internal flags via pin ERR_N …continued
Internal
flag
Flag is available on pin ERR_N[1]
Flag is cleared
Wake-up
source
in Normal mode (before the fourth
on leaving Normal mode
dominant-to-recessive edge on pin TXD[2])
Bus failure in Normal mode (after the fourth
on re-entering Normal mode or by
dominant-to-recessive edge on pin TXD[2]) setting the Pwon flag
Local failure in Listen-only mode (coming from Normal
mode)
on entering Normal mode or when RXD
is dominant while TXD is recessive
(provided that all local failures are
resolved) or by setting the Pwon flag
[1] Pin ERR_N is an active-LOW output, so a LOW-level indicates a set flag and a HIGH-level indicates a
cleared flag. Allow pin ERR_N to stabilize for at least 8 μs after changing operating modes.
[2] Allow for a TXD dominant time of at least 4 μs per dominant-recessive cycle.
6.2.1
UVNOM flag
UVNOM is the VCC and VIO undervoltage detection flag. The flag is set when the voltage on
pin VCC drops below Vuvd(VCC) for longer than tdet(uv), or when the voltage on pin VIO drops
below Vuvd(VIO) for longer than tdet(uv). When the UVNOM flag is set, the transceiver enters
Sleep mode to save power and to ensure the bus is not disturbed. In Sleep mode the
voltage regulators connected to pin INH are disabled, avoiding any extra power
consumption that might be generated as a result of a short-circuit condition.
Any wake-up request, setting the Pwon flag or a LOW-to-HIGH transition on STB_N will
clear UVNOM and the timers, allowing the voltage regulators to be reactivated (at least until
UVNOM is set again). UVNOM will also be cleared if both VCC and VIO recover for longer
than trec(uv). The transceiver will then switch to the operating mode indicated by the logic
levels on pins STB_N and EN (see Table 3).
6.2.2
UVBAT flag
UVBAT is the VBAT undervoltage detection flag. This flag is set when the voltage on
pin VBAT drops below Vuvd(VBAT). When UVBAT is set, the transceiver will try to enter
Standby mode to save power and will disengage from the bus (zero load). UVBAT is
cleared when the voltage on pin VBAT recovers. The transceiver will then switch to the
operating mode indicated by the logic levels on pins STB_N and EN (see Table 3).
6.2.3 Pwon flag
Pwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT recovers
after previously dropping below Vuvd(VBAT) (usually because the battery was
disconnected). Setting the Pwon flag clears the UVNOM flag and timers. The Wake and
Wake-up Source flags are set to ensure consistent system power-up under all supply
conditions. In Listen-only mode the Pwon flag can be polled via pin ERR_N (see Table 4).
The flag is cleared when the transceiver enters Normal mode.
6.2.4 Wake flag
The Wake flag is set when the transceiver detects a local or remote wake-up request. A
local wake-up request is detected when the logic level on pin WAKE changes, and the
new level remains stable for at least twake(min). A remote wake-up request is triggered by
two bus dominant states of at least tbus(dom), with the first dominant state followed by a
recessive state of at least tbus(rec) (provided the complete dominant-recessive-dominant
TJA1043_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 30 March 2010
© NXP B.V. 2010. All rights reserved.
8 of 26







TJA1043 equivalent, schematic
NXP Semiconductors
www.DataSheet4U.com
TJA1043
High-speed CAN transceiver
Table 8. Dynamic characteristics; …continued
VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 Ω; Tvj = 40 °C to +150 °C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device[1].
Symbol
Parameter
Conditions
Min Typ Max
twake(busrec)
tto(wake)bus
twake
bus recessive wake-up time
bus wake-up time-out time
wake-up time
Standby or Sleep mode; VBAT = 12 V 0.5
0.5
1.75
-
5
2
in response to a falling or rising edge 5 25 50
on pin WAKE; Standby or Sleep
mode
Unit
μs
ms
μs
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
TXD
CANH
HIGH
LOW
CANL
VO(dif)(bus)
RXD
0.3VIO
td(TXD-busdom)
td(TXD-busrec)
tPD(TXD-RXD)
td(busdom-RXD)
Fig 5. CAN transceiver timing diagram
0.9 V
dominant
0.5 V
0.7VIO
recessive
HIGH
LOW
tPD(TXD-RXD)
td(busrec-RXD)
015aaa025
TJA1043_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 30 March 2010
© NXP B.V. 2010. All rights reserved.
16 of 26










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