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PDF ( 数据手册 , 数据表 ) AD9148

零件编号 AD9148
描述 TxDAC+ Digital-to-Analog Converter
制造商 Analog Devices
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AD9148 数据手册, 描述, 功能
Data Sheet
Quad 16-Bit,1 GSPS,
TxDAC+ Digital-to-Analog Converter
AD9148
FEATURES
Single-carrier W-CDMA ACLR = 80 dBc at 150 MHz IF
Channel-to-channel isolation > 90 dB
Analog output
Adjustable 8.7 mA to 31.7 mA
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator eases data interface
On-chip fine complex NCO allows carrier placement
anywhere in DAC bandwidth
High performance, low noise PLL clock multiplier
Multiple chip synchronization interface
Programmable digital inverse sinc filter
Auxiliary DACs allow for offset control
Gain DACs allow for I and Q gain matching
Programmable I and Q phase compensation
Digital gain control
Flexible LVDS digital I/F supports 32- or 16-bit bus width
196-ball CSP_BGA, 12 mm × 12 mm
APPLICATIONS
Wireless infrastructure
LTE, TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM
MIMO/transmit diversity
Digital high or low IF synthesis
GENERAL DESCRIPTION
The AD9148 is a quad, 16-bit, high dynamic range, digital-to-
analog converter (DAC) that provides a sample rate of 1000 MSPS.
This device includes features optimized for direct conversion
transmit applications, including gain, phase, and offset compen-
sation. The DAC outputs are optimized to interface seamlessly with
analog quadrature modulators such as the ADL5371/ADL5372/
ADL5373/ADL5374/ADL5375. A serial peripheral interface (SPI)
is provided for programming of the internal device parameters.
Full-scale output current can be programmed over a range of 8.7 mA
to 31.7 mA. The device operates from 1.8 V and 3.3 V supplies
for a total power consumption of 3 W at the maximum sample
rate. The AD9148 is enclosed in a 196-ball chip scale package ball
grid array with the option of an attached heat spreader.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals from baseband
to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. The LVDS data input interface includes FIFO to ease input
timing.
COMPLEX BASEBAND
TYPICAL SIGNAL CHAIN
COMPLEX IF
RF
DC
FPGA/ASIC/DSP
fIF
DIGITAL INTERPOLATION FILTERS
↑2 ↑2 ↑2
DAC1
↑2 ↑2 ↑2
DAC2
LO ± fIF
POST DAC
ANALOG FILTER
AQM
LO
PA
↑2 ↑2 ↑2
DAC3
↑2 ↑2 ↑2
DAC4
POST DAC
LO
AQM
PA
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.







AD9148 pdf, 数据表
Data Sheet
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK CYCLES)
1× Interpolation (with or Without Coarse Modulation)
2× Interpolation (with or Without Coarse Modulation)
4× Interpolation (with or Without Coarse Modulation)
8× Interpolation (with or Without Coarse Modulation)
Inverse Sinc (1× Interpolation)
Inverse Sinc (2× Interpolation)
Inverse Sinc (4× Interpolation)
Inverse Sinc (8× Interpolation)
Fine Modulation
Power–Up Time
Table 4. Maximum Rate
Interface Mode
Dual Port Mode
Single Port Mode or Byte Mode
fINTERFACE
620
1200
AD9148
Min Typ Max Unit
64 Cycles
125 Cycles
254 Cycles
508 Cycles
10 Cycles
20 Cycles
40 Cycles
80 Cycles
12 Cycles
100 ms
Maximum Rate (MSPS)
fDATA
fHB1
fHB2
310 620 1000
300 600 1000
fHB3
1000
1000
fDAC
1000
1000
DATA
PORT A
INPUT
LATCH
DATA
ASSEMBLER
32
32
FIFO A
2× 2× 2×
DATAPATH
32 DAC1
AND
DAC2
DCIA
WRITE PTR A
CLK GENERATOR
AND DISTRIBUTOR
DATAPATH
DACCLK
DCIB
ONE DCI
WRITE PTR B
DATA
PORT B
INPUT
LATCH
DATA
ASSEMBLER
32 32
32 DAC3
2× 2× 2×
AND
FIFO B
DAC4
fINTERFACE
INTERFACE
MODE
fDATA
fHB1
fHB2
fHB3
Figure 3. Defining Maximum Rates
fDAC
Rev. B | Page 7 of 72







AD9148 equivalent, schematic
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–30
–35 fDATA = 200MSPS, SECOND HARMONIC
–40
fDATA = 200MSPS, THIRD HARMONIC
fDATA = 310MSPS, SECOND HARMONIC
–45 fDATA = 310MSPS, THIRD HARMONIC
–50
–55
–60
–65
–70
–75
–80
–85
–90
0
50 100 150 200 250 300
fOUT (MHz)
Figure 6. Harmonic Level vs. fOUT over fDATA, 2× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
–30
–35 fDATA = 150MSPS, SECOND HARMONIC
–40
fDATA = 150MSPS, THIRD HARMONIC
fDATA = 250MSPS, SECOND HARMONIC
–45 fDATA = 250MSPS, THIRD HARMONIC
–50
–55
–60
–65
–70
–75
–80
–85
–90
0
50 100 150 200 250 300 350 400 450 500
fOUT (MHz)
Figure 7. Harmonic Level vs. fOUT over fDATA, 4× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
–30
–35 fDATA = 125MSPS, SECOND HARMONIC
–40 fDATA = 125MSPS, THIRD HARMONIC
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
0
50 100 150 200 250 300 350 400 450 500
fOUT (MHz)
Figure 8. Harmonic Level vs. fOUT, 8× Interpolation over fDATA = 125 MSPS,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
AD9148
–30
–35 fDATA = 200MSPS, fDATA + fOUT
–40 fDATA = 310MSPS, fDATA + fOUT
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
0
50 100 150 200 250 300
fOUT (MHz)
Figure 9. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
–30
–35 fDATA = 150MSPS, fDATA + fOUT
–40 fDATA = 250MSPS, 2fDATA fOUT
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
0
50 100 150 200 250 300 350 400 450 500
fOUT (MHz)
Figure 10. Highest Digital Spur vs. fOUT over fDATA, 4× Interpolation,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
–30
–35
–40
–45
–50
–55
–60
–65 fDATA = 125MSPS, fDATA + fOUT
–70
–75
–80
–85
–90
0
50 100 150 200 250 300 350 400 450 500
fOUT (MHz)
Figure 11. Highest Digital Spur vs. fOUT, 8× Interpolation, fDATA = 125 MSPS,
Digital Scale = 0 dBFS, Full-Scale Current = 20 mA
Rev. B | Page 15 of 72










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