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PDF ( 数据手册 , 数据表 ) ADF4158

零件编号 ADF4158
描述 Direct Modulation/Waveform Generating 6.1 GHz Fractional-N Frequency Synthesizer
制造商 Analog Devices
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ADF4158 数据手册, 描述, 功能
Data Sheet
Direct Modulation/Waveform Generating,
6.1 GHz Fractional-N Frequency Synthesizer
ADF4158
FEATURES
GENERAL DESCRIPTION
Radio frequency (RF) bandwidth to 6.1 GHz
25-bit fixed modulus allows subhertz frequency resolution
Frequency and phase modulation capability
Sawtooth and triangular waveforms in the frequency domain
Parabolic ramp
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay
Ramp frequency readback
Ramp interruption
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Cycle slip reduction for faster lock times
Switched bandwidth fast-lock mode
Qualified for automotive applications
APPLICATIONS
The ADF4158 is a 6.1 GHz fractional-N frequency synthesizer
with direct modulation and waveform generation capability. It
contains a 25-bit fixed modulus, allowing subhertz resolution at
6.1 GHz. It consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. There is a sigma-delta (Σ-Δ) based fractional
interpolator to allow programmable fractional-N division. The
INT and FRAC registers define an overall N-divider as N = INT +
(FRAC/225).
The ADF4158 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. There are also
a number of frequency sweep modes available that generate
various waveforms in the frequency domain, for example,
sawtooth and triangular waveforms. The ADF4158 features
cycle slip reduction circuitry, which leads to faster lock times,
without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
Frequency modulated continuous wave (FMCW) radar
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP
RSET
ADF4158
REFIN
MUXOUT
CE
TXDATA
×2
DOUBLER
5-BIT
R-COUNTER
÷2
DIVIDER
HIGH-Z
OUTPUT
MUX
VDD
DGND
VDD
RDIV
NDIV
LOCK
DETECT
+ PHASE
FREQUENCY
DETECTOR
REFERENCE
CHARGE
PUMP
CSR
FLO SWITCH
N-COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
SW2
CP
SW1
RFINA
RFINB
CLK
DATA
LE
32-BIT
DATA
REGISTER
FRACTION MODULUS
REG
225
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. G
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADF4158 pdf, 数据表
ADF4158
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
CPGND 1
AGND 2
AGND 3
RFINB 4
RFINA 5
AVDD 6
PIN 1
INDICATOR
ADF4158
TOP VIEW
(Not to Scale)
18 SDVDD
17 MUXOUT
16 LE
15 DATA
14 CLK
13 CE
Data Sheet
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
4
RFINB
Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass capacitor,
typically 100 pF.
5
RFINA
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
6, 7, 8
AVDD
Positive Power Supply for the RF Section. Place decoupling capacitors to the digital ground plane as close as possible
to this pin. AVDD must have the same voltage as DVDD.
9
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ.
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
10
DGND
Digital Ground.
11
SDGND
Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator.
12
TXDATA
Tx Data Pin. Provide data to be transmitted in FSK or PSK mode on this pin.
13 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode.
14 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift
register on the CLK rising edge. This input is a high impedance CMOS input.
15
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a high
impedance CMOS input.
16 LE Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the eight latches,
with the latch being selected using the control bits.
17 MUXOUT Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
18
SDVDD
Power Supply Pin for the Digital Σ-Δ Modulator. This pin should be the same voltage as AVDD. Place decoupling
capacitors to the ground plane as close as possible to this pin.
19
DVDD
Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close as
possible to this pin. DVDD must have the same voltage as AVDD.
20 , 21
SW1, SW2 Switches for Fast Lock.
22 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to
5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
23 RSET Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship
between ICP and RSET is
I CPmax
=
25.5
RSET
where:
ICPmax = 5 mA.
RSET = 5.1 kΩ.
24 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the external VCO.
25
EPAD
Exposed Paddle. The LFCSP has an exposed paddle that must be connected to GND.
Rev. G | Page 8 of 36







ADF4158 equivalent, schematic
ADF4158
LSB FRAC REGISTER (R1) MAP
With Register R1 DB[2:0] set to [0, 0, 1], the on-chip LSB FRAC
register is programmed as shown in Figure 24.
13-Bit LSB FRAC Value
These 13 bits, along with Bits DB[14:3] in the FRAC/INT register
(Register R0), control what is loaded as the FRAC value into the
fractional interpolator. This is part of what determines the overall
feedback division factor. It is also used in Equation 2. These 13 bits
Data Sheet
are the least significant bits (LSB) of the 25-bit FRAC value, and
Bits DB[14:3] in the INT/FRAC register are the most significant
bits (MSB). See the RF Synthesizer: A Worked Example section
for more information.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
RESERVED
13-BIT LSB FRACTIONAL VALUE
(FRAC) (DBB)
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)
LSB FRACTIONAL VALUE
F13 F12 .......... F2 F1 (FRAC)*
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 8188
1 1 .......... 0 1 8189
1 1 .......... 1 0 8190
1 1 .......... 1 1 8191
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R0, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER R1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 24. LSB FRAC Register (R1) Map
Rev. G | Page 16 of 36










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