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PDF ( 数据手册 , 数据表 ) DAC1403D160

零件编号 DAC1403D160
描述 Dual 14 bits DAC
制造商 NXP Semiconductors
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DAC1403D160 数据手册, 描述, 功能
DAC1403D160
www.DataSheet4U.com
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating
Rev. 02 — 14 August 2008
Product data sheet
1. General description
The DAC1403D160 is optimized to reduce architecture complexity and overall system
cost. It leads to dynamic performance in multi-carrier support, because of its direct IF
conversion capabilities. With an internal sampling rate of up to 160 MHz, DAC1403D160
is an extremely competitive solution for broadband wireless systems transmitters, as well
as a wide range of applications.
2. Features
I Dual 14-bit resolution
I Spurious-Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz
I Input data rate up to 80 MHz
I 2 × interpolation filter
I Output data rate up to 160 MHz
I Single 3.3 V power supply
I Low noise capacitor-free integrated Phase-Locked Loup (PLL)
I Low power dissipation
I HTQFP80 package
I Ambient temperature from 40 °C to +85 °C
3. Applications
I Broadband wireless systems
I Digital radio links
I Cellular base stations
I Instrumentation
I Cable modem
I Cable Modem Termination System (CMTS)/Data Over Cable Service Interface
Specification (DOCSIS)







DAC1403D160 pdf, 数据表
NXP Semiconductors
DAC1403D160
www.DataSheet
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating
10. Characteristics
Table 5. Characteristics
VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = 40 °C to +85 °C; typical values measured at
VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 °C; dynamic parameters measured using output schematic given in
Figure 10; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ Max
Unit
Supplies
VCCD
VCCA
ICCD
ICCA
Ptot
digital supply voltage
analog supply voltage
digital supply current
analog supply current
total power dissipation
Clock inputs (CLK and CLKN)
fclk = 80 MHz;
fIOUT = fQOUT = 5 MHz
3.0 3.3 3.6 V
3.0 3.3 3.6 V
-
55 65
mA
-
73 85
mA
-
422 540
mW
VI(cm)
common-mode input
voltage
- 1.65 - V
Vi(dif)(p-p)
peak-to-peak differential
input voltage
- 1.0 - V
Analog outputs (IOUT, IOUTN, QOUT and QOUTN)
IO(fs)
full-scale output current differential outputs
Ro output resistance
Co output capacitance
Digital inputs (I0 to I13, Q0 to Q13 and GAPD)
4
[1] -
[1] -
- 20
150 -
3-
mA
k
pF
VIL LOW-level input voltage
VIH HIGH-level input voltage
IIL LOW-level input current
IIH HIGH-level input current
Reference voltage output (GAPOUT)
VIL = 0.3 VCCD
VIH = 0.7 VCCD
DGND -
0.7 VCCD -
-5
-5
0.3 VCCD V
VCCD
V
- µA
- µA
VGAPOUT
IGAPOUT
VGAPOUT
voltage on pin GAPOUT
current on pin GAPOUT
voltage variation on pin
GAPOUT
external voltage
- 1.31 - V
- 1 - µA
- ±133 - ppm/°C
Clock timing inputs (CLK and CLKN)
fclk clock frequency
tw(clk)H
HIGH clock pulse width
tw(clk)L
LOW clock pulse width
Input timing (I0 to I13 and Q0 to Q13); see Figure 5
- - 80 MHz
5 - - ns
5 - - ns
th(i) input hold time
tsu(i) input set-up time
Output timing (IOUT, IOUTN, QOUT, QOutN)
1.1 -
1.5 -
3.4 ns
+0.7 ns
ts settling time
to = ± 0.5 LSB
[1] -
43 -
ns
DAC1403D160_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
8 of 19







DAC1403D160 equivalent, schematic
NXP Semiconductors
DAC1403D160
www.DataSheet4U.com
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating
13. Abbreviations
Table 9. Abbreviations
Acronym
Description
BW BandWidth
FIR Finite Impulse Response
IF Intermediate Frequency
LSB Least Significant Bit
MSB
Most Significant Bit
PLL Phase-Locked Loop
PMOS
Positive-Metal Oxide Semiconductor
14. Glossary
14.1 Static parameters
DNL — Differential Non-Linearity. The difference between the ideal and the measured
output value between successive DAC codes.
INL — Integral Non-Linearity. The deviation of the transfer function from a best-fit straight
line (linear regression computation).
14.2 Dynamic parameters
IMD2 — Second-order intermodulation distortion. From a dual-tone digital input sine wave
(these two frequencies are close together), the intermodulation distortion product IMD2 is
the ratio of the RMS value of either tone and the RMS value of the worst 2nd-order
intermodulation product.
IMD3 — Third-order intermodulation distortion. From a dual-tone digital input sine wave
(these two frequencies are close together), the intermodulation distortion product IMD3 is
the ratio of the RMS value of either tone and the RMS value of the worst 3rd-order
intermodulation product.
S/N — Signal-to-Noise ratio. The ratio of the RMS value of the reconstructed output sine
wave to the RMS value of the noise excluding the harmonics and the DC component.
THD — Total Harmonic Distortion. The ratio of the RMS value of the harmonics of the
output frequency to the RMS value of the output sine wave. Usually, the calculation of
THD is done on the first 5 harmonics.
SFDR — Spurious-Free Dynamic Range. The ratio of the RMS value of the reconstructed
output sine wave and the RMS value of the largest spurious (harmonic and non-harmonic,
excluding DC component) observed in the frequency domain.
DAC1403D160_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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