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零件编号 | DAC1003D160 | ||
描述 | Dual 10 bits DAC | ||
制造商 | NXP Semiconductors | ||
LOGO | |||
1 Page
DAC1003D160
www.DataSheet4U.com
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Rev. 02 — 13 August 2008
Product data sheet
1. General description
The DAC1003D160 is optimized to reduce architecture complexity and overall system
cost. The Digital-to-Analog Converter (DAC) leads dynamic performance in multi-carrier
support because of its direct IF conversion capabilities. With an internal sampling rate up
to 160 MHz, the DAC1003D160 is an extremely competitive solution for broadband
wireless systems transmitters, as well as a wide range of applications.
2. Features
I Dual 10-bit resolution
I Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz
I Input data rate up to 80 MHz
I 2 × interpolation filter
I Output data rate up to 160 Mhz
I Single 3.3 V power supply
I Low noise capacitor free integrated Phase-Locked Loop (PLL)
I Low power dissipation
I HTQFP80 package
I Ambient temperature from −40 °C to +85 °C
3. Applications
I Broadband wireless systems
I Digital radio links
I Cellular base stations
I Instrumentation
I Cable modems
I Cable Modem Termination System (CMTS)/Data Over Cable Service Interface
Specification (DOCSIS)
NXP Semiconductors
DAC1003D160
www.DataSheet4U.com
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Table 5. Characteristics …continued
VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = −40 °C to +85 °C; typical values measured at
VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 °C; dynamic parameters measured using output schematic given in
Figure 10; unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
ICCA analog supply current
Ptot total power dissipation
Clock inputs (CLK and CLKN)
fclk = 80 MHz;
fIOUT = fQOUT = 5 MHz
-
73 85
mA
-
422 540
mW
VI(cm)
common-mode input
voltage
- 1.65 - V
Vi(dif)(p-p) peak-to-peak differential
input voltage
- 1.0 - V
Analog outputs (IOUT, IOUTN, QOUT and QOUTN)
IO(fs)
full-scale output current differential outputs
Ro output resistance
Co output capacitance
Digital inputs (I0 to I9, Q0 to Q9 and GAPD)
4
[1] -
[1] -
- 20
150 -
3-
mA
kΩ
pF
VIL LOW-level input voltage
VIH HIGH-level input voltage
IIL LOW-level input current
IIH HIGH-level input current
Reference voltage output (GAPOUT)
VIL = 0.3 VCCD
VIH = 0.7 VCCD
DGND -
0.7 VCCD -
-5
-5
0.3 VCCD V
VCCD
-
V
µA
- µA
VGAPOUT
IGAPOUT
∆VGAPOUT
voltage on pin GAPOUT
current on pin GAPOUT
voltage variation on pin
GAPOUT
external voltage
- 1.31 - V
- 1 - µA
- ±133 - ppm/°C
Clock timing inputs (CLK and CLKN)
fclk clock frequency
tw(clk)H
HIGH clock pulse width
tw(clk)L
LOW clock pulse width
Input timing (I0 to I9 and Q0 to Q9); see Figure 5
- 80 MHz
5 --
ns
5 --
ns
th(i) input hold time
tsu(i) input set-up time
Output timing (IOUT, IOUTN, QOUT, QOUTN)
1.1 -
−1.5 -
3.4
+0.7
ns
ns
ts settling time
to ± 0.5 LSB
[1] -
Digital filter specification (FIR); order N = 42 see Figure 6 and 7 and Table 7
16 -
ns
fdata data rate
- - 80 MHz
αripple(pb) pass-band ripple
fdata/fclk; 0.005 dB attenuation - 0.405 -
Bp power bandwidth
fdata/fclk; 3 dB attenuation
- 0.479 -
αstpb
stop-band attenuation
fdata/fclk = 0.6 dB to 1 dB
- 69 - dB
td(grp)
group delay time
- 11 Tclk - ns
Analog signal processing
INL integral non-linearity
- ±0.2 - LSB
DNL
differential non-linearity
- ±0.1 - LSB
DAC1003D160_2
Product data sheet
Rev. 02 — 13 August 2008
© NXP B.V. 2008. All rights reserved.
8 of 19
NXP Semiconductors
DAC1003D160
www.DataSheet4U.com
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
13. Abbreviations
Table 9. Abbreviations
Acronym
Description
FIR Finite Impulse Response
IF Intermediate Frequency
LSB Least Significant Bit
MSB
Most Significant Bit
PLL Phase-Locked Loop
PMOS
Positive-Metal Oxide Semiconductor
14. Glossary
14.1 Static parameters
DNL — Differential Non-Linearity. The difference between the ideal and the measured
output value between successive DAC codes.
INL — Integral Non-Linearity. The deviation of the transfer function from a best-fit straight
line (linear regression computation).
14.2 Dynamic parameters
IMD2 — Second-order intermodulation distortion. From a dual-tone digital input sine wave
(these two frequencies are close together), the intermodulation distortion product IMD2 is
the ratio of the RMS value of either tone and the RMS value of the worst 2nd-order
intermodulation product.
IMD3 — Third-order intermodulation distortion. From a dual-tone digital input sine wave
(these two frequencies are close together), the intermodulation distortion product IMD3 is
the ratio of the RMS value of either tone and the RMS value of the worst 3rd-order
intermodulation product.
SFDR — Spurious Free Dynamic Range. The ratio between the RMS value of the
reconstructed output sine wave and the RMS value of the largest spurious observed
(harmonic and non-harmonic, excluding DC component) in the frequency domain.
S/N — Signal-to-Noise ratio. The ratio of the RMS value of the reconstructed output sine
wave to the RMS value of the noise excluding the harmonics and the DC component.
THD — Total Harmonic Distortion. The ratio of the RMS value of the harmonics of the
output frequency to the RMS value of the output sine wave. Usually, the calculation of
THD is done on the first 5 harmonics.
DAC1003D160_2
Product data sheet
Rev. 02 — 13 August 2008
© NXP B.V. 2008. All rights reserved.
16 of 19
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页数 | 19 页 | ||
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零件编号 | 描述 | 制造商 |
DAC1003D160 | Dual 10 bits DAC | NXP Semiconductors |
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