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PDF ( 数据手册 , 数据表 ) K7A163630B

零件编号 K7A163630B
描述 512Kx36 & 1Mx18 Synchronous SRAM
制造商 SAMSUNG ELECTRONICS
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K7A163630B 数据手册, 描述, 功能
K7A163630B
K7A161830B
512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com
18Mb B-die Sync. SRAM Specification
100TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 - July 2005
Rev 1.0







K7A163630B pdf, 数据表
K7A163630B
K7A161830B
512Kx36 & 1Mx18 SynchronouwswwS.DRatAaShMeet4U.com
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED
HXXXLX X
N/A
L LXLXX X
LXHLXX X
L LXXLX X
N/A
N/A
N/A
L XHX LX X
N/A
LHL LXX X
LHLHLX L
LHLHLX H
XXXHH L H
External Address
External Address
External Address
Next Address
HXXXHL H
XXXHH L L
HXXXHL L
Next Address
Next Address
Next Address
XXXHHH H
Current Address
HXXXHH H
XXXHHH L
HXXXHH L
Current Address
Current Address
Current Address
Notes : 1. X means "Dont Care". 2. The rising edge of clock is symbolized by .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
OPERATION
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
WRITE TRUTH TABLE(x36)
GW
BW
WEa
WEb
WEc
WEd
HH X X X X
H L HHHH
HL LHHH
H L H L HH
HLHHL L
HL L L L L
LXXXXX
Notes : 1. X means "Dont Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
OPERATION
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
WRITE TRUTH TABLE(x18)
GW
BW
WEa
WEb
HHXX
H L HH
HL LH
HLHL
HL L L
LXXX
OPERATION
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
Notes : 1. X means "Dont Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
- 8 - July 2005
Rev 1.0







K7A163630B equivalent, schematic
CLOCK
ADSP
tSS tSH
TIMING WAVEFORM OF POWER DOWN CYCLE
tCH tCL
tCYC
ADSC
ADDRESS
tAS tAH
A1
WRITE
CS
tCSS
tCSH
ADV
OE
Data In
Data Out
ZZ
tOE
tLZOE
Q1-1
tHZC
tPDS
ZZ Setup Cycle
Sleep State
tPUS
ZZ Recovery Cycle
A2
tWS
tWH
tHZOE
D2-1
D2-2
Normal Operation Mode
Dont Care
Undefined










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