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零件编号 | QL3060 | ||
描述 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | ||
制造商 | QuickLogic Corporation | ||
LOGO | |||
1 Page
QL3060 pASIC 3 FPGA Data Sheet
• • • • • • 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
Device Highlights
High Performance & High Density
• 60,000 Usable PLD Gates with 316 I/Os
www.Da•taS3h0ee0t4MU.cHozm16-bit Counters,
400 MHz Datapaths
• 0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
• 100% routable with 100% utilization and
complete pin-out stability
• Variable-grain logic cells provide high
performance and 100% utilization
• Comprehensive design tools include high
quality Verilog/VHDL synthesis
Eight Low-Skew Distributed
Networks
• Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
• Six global clock/control networks available
to the logic cell F1, clock set, and reset
inputs and the input and I/O register clock,
reset, and enable inputs as well as the output
enable control — each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
High Performance
• Input + logic cell + output total delays
under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
Advanced I/O Capabilities
• Interfaces with both 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 316 I/O Pins
• 308 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
• Eight high-drive input/distributed
network pins
Figure 1: 1,584 pASIC 3 Logic Cells
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3060 pASIC 3 FPGA Data Sheet Rev D
Kv and Kt Graphs
www.DataSheet4U.com
1.1000
1.0800
1.0600
1.0400
1.0200
1.0000
0.9800
0.9600
0.9400
0.9200
3
Voltage Factor vs. Supply Voltage
3.1 3.2 3.3 3.4 3.5
Supply Voltage (V)
Figure 3: Voltage Factor vs. Supply Voltage
3.6
Temperature Factor vs. Operating Temperature
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-60 -40 -20
0
20 40
Junction Temperature C
60
80
Figure 4: Temperature Factor vs. Operating Temperature
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• www.quicklogic.com
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© 2002 QuickLogic Corporation
QL3060 pASIC 3 FPGA Data Sheet Rev D
456 PBGA Pinout Table
456
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
www.DataSheet4AU1.c3 om
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 11: 456 PBGA Pinout Table
456 Function 456 Function 456
B26 STM D25
I/O
H4
C1 I/O D26 I/O H5
C2 I/O E1 I/O H22
C3 I/O E2 I/O H23
C4 TDO E3
I/O H24
C5 I/O E4 I/O H25
C6
I/O
E5
GND
H26
C7 I/O E6 VCC J1
C8 I/O E7 GND J2
C9 I/O E8 NC J3
C10 I/O
E9 GND J4
C11 I/O E10 I/O
J5
C12 I/O E11 GND J22
C13 I/O E12 GND J23
C14 I/O E13 VCC J24
C15 I/O E14 GND J25
C16 I/O E15 GND J26
C17 I/O E16 GND K1
C18 I/O E17 NC
K2
C19 I/O E18 GND K3
C20 I/O E19 NC
K4
C21 I/O E20 GND K5
C22 I/O E21 VCC K22
C23 I/O E22 GND K23
C24 I/O E23 I/O K24
C25 TCK E24 I/O K25
C26 I/O E25 I/O K26
D1 I/O E26 I/O L1
D2 I/O F1 I/O L2
D3 I/O F2 I/O L3
D4 GND F3 I/O L4
D5 I/O F4 NC L5
D6 NC F5 VCC L11
D7 I/O F22 VCC L12
D8 I/O F23 NC L13
D9
GND
F24
I/O
L14
D10 I/O F25 I/O L15
D11 I/O F26 I/O L16
D12 GND
G1
I/O L22
D13 I/O G2 I/O L23
D14 I/O G3 I/O L24
D15 GND
G4
I/O L25
D16 I/O G5 NC L26
D17
I/O
G22
GND
M1
D18 GND G23
I/O
M2
D19 I/O G24 I/O
M3
D20 I/O G25 I/O
M4
D21 NC G26 I/O
M5
D22 I/O H1 I/O M11
D23 GND
H2
I/O M12
D24 I/O H3 I/O M13
(Sheet 1 of 2)
Function
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
GND
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
NC
I/O
I/O
I/O
I/O
ACLK / I
GCLK/I
I/O
NC
GND
GND/THERM
GND/THERM
GND/THERM
456
M14
M15
M16
M22
M23
M24
M25
M26
N1
N2
N3
N4
N5
N11
N12
N13
N14
N15
N16
N22
N23
N24
N25
N26
P1
P2
P3
P4
P5
P11
P12
P13
P14
P15
P16
P22
P23
P24
P25
P26
R1
R2
R3
R4
R5
R11
R12
R13
R14
R15
R16
Function
GND/THERM
GND/THERM
GND/THERM
NC
NC
I/O
I/O
I/O
GCLK/I
I/O
I/O
GCLK/I
VCC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
NC
GCLK / I
GCLK / I
I/O
ACLK / I
I/O
I/O
I/O
NC
NC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
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www.quicklogic.com
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© 2002 QuickLogic Corporation
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页数 | 19 页 | ||
下载 | [ QL3060.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
QL3060 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | QuickLogic Corporation |
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