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PDF ( 数据手册 , 数据表 ) H55S1262EFP-75M

零件编号 H55S1262EFP-75M
描述 128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O
制造商 Hynix Semiconductor
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H55S1262EFP-75M 数据手册, 描述, 功能
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128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O
Specification of
128M (8Mx16bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 2,097,152 x16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 /Aug. 2009
1







H55S1262EFP-75M pdf, 数据表
11
128Mbit (8Mx16bit) MobilewwSwD.DRataMSheemet4oUr.cyom
H55S1262EFP Series
BALL DESCRIPTION
SYMBOL
CLK
CKE
CS
BA0, BA1
A0 ~ A11
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
VDD/VSS
VDDQ/VSSQ
NC
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
SUPPLY
SUPPLY
-
DESCRIPTION
Clock : The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Clock Enable : Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among (deep) power down, suspend or self refresh
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask : Controls output buffers in read mode and masks input data in write
mode
Data Input/Output : Multiplexed data input/output pin
Power supply for internal circuits
Power supply for output buffers
No connection
Rev 1.2 /Aug. 2009
8







H55S1262EFP-75M equivalent, schematic
11
128Mbit (8Mx16bit) MobilewwSwD.DRataMSheemet4oUr.cyom
H55S1262EFP Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 BA0 A11 A10
0000
A9
OP Code
A8 A7 A6 A5 A4 A3 A2 A1 A0
00
CAS Latency BT Burst Length
OP Code
A9
0
1
Write Mode
Burst Read and Burst Write
Burst Read and Single Write
Burst Type
A3 Burst Type
0 Sequential
1 Interleave
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
A2 A1 A0
00 0
00 1
01 0
01 1
10 0
10 1
1 10
1 11
Burst Length
A3 = 0
A3=1
11
22
44
88
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Full page
Reserved
Rev 1.2 /Aug. 2009
16










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