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PDF ( 数据手册 , 数据表 ) STE2004

零件编号 STE2004
描述 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER
制造商 STMicroelectronics
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STE2004 数据手册, 描述, 功能
STE2004www.DataSheet4U.com
102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER
1 FEATURES
102 x 65 bits Display Data RAM
Programmable MUX rate
Programmable Frame Rate
X,Y Programmable Carriage Return
Dual Partial Display Mode
Row by Row Scrolling
N-Line Inversion
Automatic data RAM Blanking procedure
Selectable Input Interface:
• I2C Bus Fast and Hs-mode (read and write)
• 68000 & 8080 Parallel Interfaces (read and write)
• 3-lines and 4-lines SPI Interface (read and write)
• 3-lines 9 bit Serial Interface (read and write)
Fully Integrated Oscillator requires no external
components
CMOS Compatible Inputs
Fully Integrated Configurable LCD bias voltage
generator with:
• Selectable multiplication factor (up to 5X)
• Effective sensing for High Precision Output
• Eight selectable temperature compensation
coefficients
Designed for chip-on-glass (COG) applications.
Low Power Consumption, suitable for battery
operated systems
Logic Supply Voltage range from 1.7 to 3.6V
High Voltage Generator Supply Voltage range
from 1.75 to 4.5V
Display Supply Voltage range from 4.5 to 14.5V
Backward Compatibility with STE2001/2
2 DESCRIPTION
The STE2004 is a low power CMOS LCD control-
ler driver. Designed to drive a 65 rows by 102 col-
umns graphic display, it provides all necessary
functions in a single chip, including on-chip LCD
supply and bias voltages generators, resulting in a
minimum of externals components and in a very
low power consumption.
STE2004 features six standard interfaces (3-lines
Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel,
8080 parallel & I2C) for ease of interfacing with the
host micro-controller
Table 1. Order Codes
Part Numbers
Type
STE2004DIE1
STE2004DIE2
Bumped Wafers
Bumped Dice on Waffle Pack
Figure 1. Block Diagram
CO to C101
R0 to R64
OSC_IN
OSC_OUT
FR_IN
FR_OUT
VSENSE SLAVE
VLCD
VLCDSENSE
RES
VSSAUX
VDD1,2
VSS
SEL1,2
OSC
MASTER
SLAVE SYNC
BIAS VOLTAGE
GENERATOR
TIMING
GENERATOR
CLOCK
COLUMN
DRIVERS
DATA
LATCHES
ROW
DRIVERS
SHIFT
REGISTER
HIGH VOLTAGE
GENERATOR
RESET
DATA
REGISTER
65 x 102
RAM
SCROLL
LOGIC
TEST
INSTRUCTION
REGISTER
DISPLAY
CONTROL
LOGIC
I2C BUS 9 Bit SERIAL 3 & 4 Line SPI Parallel 8080 Parallel 68K
TEST_MODE
TEST_VREF
ICON_MODE
EXT
SEL 0
SEL 1
SEL 2
July 2004
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD D/C
to
DB7
CS
LR0047
Rev. 4
1/66







STE2004 pdf, 数据表
STE2004
Table 3.
BS2 BS1 BS0
000
001
010
011
100
101
110
111
The following table Bias Level for m = 65 and m = 49 are provided:
Table 4.
Symbol
V1
V2
V3
V4
V5
V6
m = 65 (1/9)
VLCD
8/9*VLCD
7/9*VLCD
2/9*V VLCD
1/9 *VLCD
VSS
www.DataSheet4U.com
n
7
6
5
4
3
2
1
0
m = 49 (1/8)
VLCD
7/8*VLCD
6/8*VLCD
2/8*VLCD
1/8*VLCD
VSS
3.6 LCD Voltage Generation
The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to
the following formula:
VLCD(T=To) = VLCDo = (Ai+VOP · B) (i=0,1,2)
with the following values:
Symbol
Ao
A1
A2
B
To
Value
2.95
6.83
10.71
0.0303
27
Unit
V
V
V
V
°C
Note
PRS = [0;0]
PRS = [0;1]
PRS = [1;0]
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits
are set to zero the internal voltage generator is switched off.
The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Mul-
tiplexing Rate. A general expression for this is:
VLCD
=
---------1-----+---------m------------
2 1 – ----1-m---
Vth
For MUX Rate m = 65 the ideal VLCD is:
VLCD(to) = 6.85 · Vth
than:
Vop
=
(---6---.--8---5--------V----t--h----–-----A----i--)
0.03
8/66







STE2004 equivalent, schematic
STE2004
Figure 20. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=6 and wMwUwX.4D9ataSheet4U.com
Y-CARRIAGE
Y Address
Da
D3 D2 D1 D0 at
0 00
0 00
0 01
0 01
0 10
0 10
0 11
0 11
1 00
X address
D0
D1
D2
0 D3
D4
D5
D6
D7
D0
D1
D2
1 D3
D4
D5
D6
D7
D0
D1
D2
0 D3
D4
D5
D6
D7
D0
D1
D2
1 D3
D4
D5
D6
D7
D0
D1
D2
0 D3
D4
D5
D6
D7
D0
D1
D2
1 D3
D4
D5
D6
D7
D0
D1
D2
0 D3
D4
D5
D6
D7
D0
D1
D2
1 D3
D4
D5
D6
D7
0 D0
00H 01H 02H 03H 04H 05H 06H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
5FH 60H 61H 62H 63H 64H 65H
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0 R55
R1 R54
R2 R53
R3 R52
R4 R51
R5 R50
R6 R49
R7 R48
R8 R47
R9 R46
R10 R45
R11 R44
R12 R43
R13 R42
R14 R41
R15 R40
R16 R39
R17 R38
R18 R37
R19 R36
R20 R35
R21 R34
R22 R33
R23 R32
R32 R23
R33 R22
R34 R21
R35 R20
R36 R19
R37 R18
R38 R17
R39 R16
R40 R15
R41 R14
R42 R13
R43 R12
R44 R11
R45 R10
R46 R9
R47 R8
R48 R7
R49 R6
R50 R5
R51 R4
R52 R3
R53 R2
R54 R1
R55 R0
R56 R56
COL
Output
Normal
Direction
Reverse
Direction
C CCC CCC
O OOO OOO
L LLL LLL
0123456
C CC C C CC
O OO O O OO
L LL L L LL
101 100 99 98 97 96 95
C CC CC C C
O OO OO O O
L LL LL L L
95 96 97 98 99 100 101
C C C C C CC
O O O O O OO
L L L L L LL
6 54 32 10
lr0270
16/66










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