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PDF ( 数据手册 , 数据表 ) W332M72V-XBX

零件编号 W332M72V-XBX
描述 32Mx72 Synchronous DRAM
制造商 White Electronic Designs
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W332M72V-XBX 数据手册, 描述, 功能
White Electronic Designs
W332M72V-XBX
www.DataSheet4U.com
32Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 32M x 72
Weight: W332M72V-XBX – 3.5 grams typical
BENEFITS
40% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 19% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Pinout compatible with lower desities
WEDPN4M72V-XB2X, WEDPN8M72V-XB2X and
WEDPN16M72V-XB2X
* This product is subject to change without notice.
GENERAL DESCRIPTION
The 256MByte (2Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 134,217,728-bit banks is organized as 8,192
rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 2Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging
one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
The 2Gb SDRAM is designed to operate at 3.3V. An auto
refresh mode is provided, along with a power-saving,
power-down mode.
Discrete Approach
11.9 11.9 11.9 11.9
11.9
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
Area
I/O
Count
5 x 265mm2 = 1328mm2
5 x 54 pins = 270 pins
ACTUAL SIZE
White Electronic Designs
W332M72V-XBX
25
32
S
A
V
I
N
G
S
800mm2
40%
219 Balls
19%
March 2006
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com







W332M72V-XBX pdf, 数据表
White Electronic Designs
W332M72V-XBX
www.DataSheet4U.com
on the I/Os subject to the logic level on the DQM inputs
two clocks earlier. If a given DQM signal was registered
HIGH, the corresponding I/Os will be High-Z two clocks
later; if the DQM signal was registered LOW, the I/Os will
provide valid data.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
selects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os
is written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command
is issued. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one
bank is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specific READ or WRITE command. A precharge of
the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of
the READ or WRITE burst, except in the full-page burst
mode, where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled or
disabled for each individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must not
issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible
time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
either fixed-length or full-page bursts. The most recently
registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. Each 512Mb SDRAM
requires 8,192 AUTO REFRESH cycles every refresh
period (tREF). Providing a distributed AUTO REFRESH
command will meet the refresh requirement and ensure that
each row is refreshed. Alternatively, 8,192 AUTO REFRESH
commands can be issued in a burst at the minimum cycle
rate (tRC), once every refresh period (tREF).
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which
must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to tRAS and
may remain in self refresh mode for an indefinite period
beyond that.
* Self refresh available in commercial and industrial temperatures only.
March 2006
Rev. 3
8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com














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