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PDF ( 数据手册 , 数据表 ) DAC101C081

零件编号 DAC101C081
描述 12-Bit Micro Power Digital-to-Analog Converter with an I2C-Compatible Interface
制造商 National Semiconductor
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DAC101C081 数据手册, 描述, 功能
December 20, 2007
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DAC121C081/ DAC121C085
12-Bit Micro Power Digital-to-Analog Converter with an
I2C-Compatible Interface
General Description
The DAC121C081 is a 12-bit, single channel, voltage-output
digital-to-analog converter (DAC) that operates from a +2.7V
to 5.5V supply. The output amplifier allows rail-to-rail output
swing and has an 8.5usec settling time. The DAC121C081
uses the supply voltage as the reference to provide the widest
dynamic output range and typically consumes 132uA while
operating at 5.0V. It is available in 6-lead TSOT and LLP
packages and provides three address options (pin se-
lectable).
As an alternative, the DAC121C085 provides nine I2C ad-
dressing options and uses an external reference. It has the
same performance and settling time as the DAC121C081. It
is available in an 8-lead MSOP.
The DAC121C081 and DAC121C085 use a 2-wire, I2C-com-
patible serial interface that operates in all three speed modes,
including high speed mode (3.4MHz). An external address
selection pin allows up to three DAC121C081 or nine
DAC121C085 devices per 2-wire bus. Pin compatible alter-
natives to the DAC121C081 are available that provide addi-
tional address options.
The DAC121C081 and DAC121C085 each have a 16-bit reg-
ister that controls the mode of operation, the power-down
condition, and the output voltage. A power-on reset circuit
ensures that the DAC output powers up to zero volts. A power-
down feature reduces power consumption to less than a
microWatt. Their low power consumption and small packages
make these DACs an excellent choice for use in battery op-
erated equipment. Each DAC operates over the extended
industrial temperature range of −40°C to +125°C.
The DAC121C081 and DAC121C085 are each part of a fam-
ily of pin compatible DACs that also provide 8 and 10 bit
resolution. For 8-bit DACs see the DAC081C081 and
DAC081C085. For 10-bit DACs see the DAC101C081 and
DAC101C085.
Features
Guaranteed Monotonicity to 12-bits
Low Power Operation: 156 µA max @ 3.3V
Extended power supply range (+2.7V to +5.5V)
I2C-Compatible 2-wire Interface which supports standard
(100kHz), fast (400kHz), and high speed (3.4MHz) modes
Rail-to-Rail Voltage Output
Very small 6-pin TSOT and LLP Packages
Key Specifications
Resolution
INL
DNL
Settling Time
Zero Code Error
Full-Scale Error
Supply Power
Normal
Power Down
12 bits
±8 LSB (max)
+0.6 / -0.5 LSB (max)
8.5 µs (max)
+10 mV (max)
−0.7 %FS (max)
380 µW (3V) / 730 µW (5V) typ
0.5 µW (3V) / 0.9 µW (5V) typ
Applications
Industrial Process Control
Portable Instruments
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Test Equipment
Pin-Compatible Alternatives
All devices are fully pin and function compatible.
Resolution TSOT-6 and LLP-6 MSOP-8 Package w/
Packages
External Reference
12-bit
DAC121C081
DAC121C085
10-bit
DAC101C081
DAC101C085
8-bit
DAC081C081
DAC081C085
Connection Diagrams
30004901
I2C® is a registered trademark of Phillips Corporation.
© 2007 National Semiconductor Corporation
300049
30004902
30004910
www.national.com







DAC101C081 pdf, 数据表
Symbol
Parameter
Conditions (Note 13)
trDA Rise time of SDA signal
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
tfDA Fall time of SDA signal
High Speed Mode, Cb = 400pF
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
trCL Rise time of SCL signal
High Speed Mode, Cb = 400pF
Standard Mode
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
Standard Mode
Rise time of SCL signal after a
Fast Mode
trCL1
repeated start condition and after an
acknowledge bit.
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
Standard Mode
tfCL Fall time of a SCL signal
Fast Mode
High Speed Mode, Cb = 100pF
High Speed Mode, Cb = 400pF
Cb
Capacitive load for each bus line (SCL
and SDA)
tSP
Pulse Width of spike suppressed
(Notes 11, 10)
Fast Mode
High Speed Mode
toutz
SDA output delay (see Section 1.9) Fast Mode
High Speed Mode
Limits
(TNyoptieca9wl) ww.D(Naot1at3eS)she9,et4U.c(oLUmimniittss)
1000
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
10 ns (min)
80 ns (max)
20 ns (min)
160 ns (max)
250 ns (max)
20+0.1Cb
250
ns (min)
ns (max)
10 ns (min)
80 ns (max)
20 ns (min)
160 ns (max)
1000
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
10 ns (min)
40 ns (max)
20 ns (min)
80 ns (max)
1000
ns (max)
20+0.1Cb
300
ns (min)
ns (max)
10 ns (min)
80 ns (max)
20 ns (min)
160 ns (max)
300 ns (max)
20+0.1Cb
300
ns (min)
ns (max)
10 ns (min)
40 ns (max)
20 ns (min)
80 ns (max)
400 pF (max)
50 ns (max)
10 ns (max)
87 270 ns (max)
38 60 ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package
input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond
the operating ratings, or the power supply polarity is reversed).
Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kresistor. Machine model is a 220 pF capacitor discharged through 0 . Charge
device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
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8







DAC101C081 equivalent, schematic
1.4.3 High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communica-
tion differ slightly from Standard-Fast mode. Figure 5 de-
scribes this in further detail. Initially, the bus begins running
in Standard-Fast mode. The master generates a Start condi-
tion and sends the 8-bit Hs master code (00001XXX) to the
DAC121C081. Next, the DAC121C081 responds with a
NACK. Once the SCL line has been pulled to a high level, the
master switches to Hs-mode by increasing the bus speed and
generating a Repeated Start condition (driving SDA low while
SCL is pulled high). At this point, the master sends the slave
address to the DAC121C081, and communication continues
as shown above in the "Basic Owpwewra.tDioant"aDSihaegerat4mU(.sceoemFigure
4).
When the master generates a Repeated Start condition while
in Hs-mode, the bus stays in Hs-mode awaiting the slave ad-
dress from the master. The bus continues to run in Hs-mode
until a Stop condition is generated by the master. When the
master generates a Stop condition on the bus, the bus must
be started in Standard-Fast mode again before increasing the
bus speed and switching to Hs-mode. ns16705
FIGURE 5. Beginning Hs-Mode Communication
30004912
1.4.4 I2C Slave (Hardware) Address
The DAC has a seven-bit I2C slave address. For the MSOP-8
version of the DAC, this address is configured by the ADR0
and ADR1 address selection inputs. For the DAC121C081,
the address is configured by the ADR0 address selection in-
put. ADR0 and ADR1 can be grounded, left floating, or tied to
VA. If desired, the address selection inputs can be set to VA/
2 rather than left floating. The state of these inputs sets the
address the DAC responds to on the I2C bus (see Table 1).
In addition to the selectable slave address, there is also a
broadcast address (1001000) for all DAC121C081's and
DAC121C085's on the 2-wire bus. When the bus is addressed
by the broadcast address, all the DAC121C081's and
DAC121C085's will respond and update synchronously. Fig-
ure 6 and Figure 7 describe how the master device should
address the DAC via the I2C-Compatible interface.
Keep in mind that the address selection inputs (ADR0 and
ADR1) are only sampled until the DAC is correctly addressed
with a non-broadcast address. At this point, the ADR0 and
ADR1 inputs TRI-STATE and the slave address is "locked".
Changes to ADR0 and ADR1 will not update the selected
slave address until the device is power-cycled.
TABLE 1. Slave Addresses
Slave Address
[A6 - A0]
0001100
0001101
0001110
0001000
0001001
0001010
1001100
1001101
1001110
1001000
DAC121C085 (MSOP-8)
DAC121C081
(TSOT & LLP) *
ADR1
ADR0
ADR0
Floating
Floating
Floating
Floating
GND
GND
Floating
GND
VA
Floating
VA
---------------
GND
GND
---------------
GND
VA ---------------
VA
Floating
---------------
VA
GND
---------------
VA VA ---------------
--------------- Broadcast Address ---------------
* Pin-compatible alternatives to the DAC121C081 options are available with additional address options.
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16










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