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PDF ( 数据手册 , 数据表 ) XC164-16

零件编号 XC164-16
描述 16-Bit Single-Chip Microcontroller
制造商 Infineon Technologies AG
LOGO Infineon Technologies AG LOGO 


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XC164-16 数据手册, 描述, 功能
User’s Manual, V2.1, March 2004
www.DataSheet4U.com
XC164-16
16-Bit Single-Chip Microcontroller
with C166SV2 Core
Volume 2 (of 2): Peripheral Units
Microcontrollers
Never stop thinking.







XC164-16 pdf, 数据表
XC164-16 Derivatives
Peripheral Unwiwtsw.D(VataoSlh.ee2t4Uo.cfo2m)
Table of Contents
Page
6.3.5
6.4
6.4.1
6.4.2
6.4.3
6.5
6.6
Register Security Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 [1]
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 [1]
Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 [1]
Reduction of Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 [1]
Flexible Peripheral Management . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 [1]
Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58 [1]
Identification Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63 [1]
7 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1]
7.1 Input Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1]
7.2 Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 [1]
7.3 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 [1]
7.4 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 [1]
7.5 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 [1]
7.6 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 [1]
7.7 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 [1]
7.8 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47 [1]
7.9 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 [1]
7.10 Port 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-60 [1]
8 Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1]
9
9.1
9.2
9.2.1
9.2.1.1
9.2.1.2
9.2.2
9.2.2.1
9.2.2.2
9.2.2.3
9.2.2.4
9.2.2.5
9.2.2.6
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.6.1
The External Bus Controller EBC . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]
External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 [1]
Timing Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]
Basic Bus Cycle Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]
Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 [1]
Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 [1]
Bus Cycle Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
A Phase - CS Change Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
B Phase - Address Setup/ALE Phase . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
C Phase - Delay Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
D Phase - Write Data Setup/MUX Tristate Phase . . . . . . . . . . . . 9-7 [1]
E Phase - RD/WR Command Phase . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
F Phase - Address/Write Data Hold Phase . . . . . . . . . . . . . . . . . 9-8 [1]
Bus Cycle Examples: Fastest Access Cycles . . . . . . . . . . . . . . . . . 9-8 [1]
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]
Configuration Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]
The EBC Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 [1]
The EBC Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 [1]
The Timing Configuration Registers TCONCSx . . . . . . . . . . . . . . 9-15 [1]
The Function Configuration Registers FCONCSx . . . . . . . . . . . . . 9-16 [1]
The Address Window Selection Registers ADDRSELx . . . . . . . . . 9-18 [1]
Definition of Address Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 [1]
User’s Manual I-4 V2.1, 2004-03







XC164-16 equivalent, schematic
XC164-16 Derivatives
Peripheral Unwiwtsw.D(aVtaoShl.ee2t4Uo.cfom2)
The General Purpose Timer Units
The interrupts of GPT1 are controlled through the Interrupt Control Registers TxIC.
These registers are not part of the GPT1 block. The input and output lines of GPT1 are
connected to pins of ports P3 and P5. The control registers for the port functions are
located in the respective port modules.
Note: The timing requirements for external input signals can be found in Section 14.1.5,
Section 14.3 summarizes the module interface signals, including pins.
f GPT
T2IN
T2EUD
T3IN
T3EUD
T4IN
T4EUD
2n: 1
T3CON.BPS1
Basic clock
T2
Mode
Control
Aux. Timer T2
U/D
Reload
Capture
T3
Mode
Control
Core Timer T3
U/D
Interrupt
Request
(T2IRQ)
Toggle Latch
T3OTL
Interrupt
Request
(T3IRQ)
T3OUT
T4
Mode
Control
Capture
Reload
Aux. Timer T4
U/D
Interrupt
Request
(T4IRQ)
mc_gpt0101_bldiax1.vsd
Figure 14-2 GPT1 Block Diagram (n = 2 … 5)
User’s Manual
GPT_X41, V2.0
14-3
V2.1, 2004-03










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