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零件编号 | R4F2164 | ||
描述 | 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series | ||
制造商 | Renesas Technology | ||
LOGO | |||
1 Page
REJ09B0429-0100
www.DataSheet4U.com
16
H8S/2164 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2400 Series
H8S/2164 R4F2164
Rev.1.00
Revision Date: Mar. 17, 2008
www.DataSheet4U.com
Rev. 1.00 Mar. 17, 2008 Page viii of xl
Section 12 Watchdog Timer (WDT) ................................................................. 311
12.1 Features.............................................................................................................................. 311
12.2 Input/Output Pins.......................................................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m...... 313
12.3 Register Descriptions......................................................................................................... 313
12.3.1 Timer Counter (TCNT)......................................................................................... 313
12.3.2 Timer Control/Status Register (TCSR)................................................................. 314
12.4 Operation ........................................................................................................................... 318
12.4.1 Watchdog Timer Mode......................................................................................... 318
12.4.2 Interval Timer Mode............................................................................................. 320
12.4.3 RESO Signal Output Timing ................................................................................ 321
12.5 Interrupt Sources................................................................................................................ 322
12.6 Usage Notes ....................................................................................................................... 323
12.6.1 Notes on Register Access ..................................................................................... 323
12.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 324
12.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 324
12.6.4 Changing Value of PSS Bit .................................................................................. 324
12.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 325
12.6.6 System Reset by RESO Signal ............................................................................. 325
Section 13 Serial Communication Interface (SCI)............................................ 327
13.1 Features.............................................................................................................................. 327
13.2 Input/Output Pins............................................................................................................... 330
13.3 Register Descriptions......................................................................................................... 330
13.3.1 Receive Shift Register (RSR) ............................................................................... 331
13.3.2 Receive Data Register (RDR)............................................................................... 331
13.3.3 Transmit Data Register (TDR).............................................................................. 331
13.3.4 Transmit Shift Register (TSR) .............................................................................. 331
13.3.5 Serial Mode Register (SMR) ................................................................................ 332
13.3.6 Serial Control Register (SCR) .............................................................................. 335
13.3.7 Serial Status Register (SSR) ................................................................................. 338
13.3.8 Smart Card Mode Register (SCMR)..................................................................... 342
13.3.9 Bit Rate Register (BRR) ....................................................................................... 343
13.4 Operation in Asynchronous Mode ..................................................................................... 347
13.4.1 Data Transfer Format............................................................................................ 348
13.4.2 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode ............................................................................................. 349
13.4.3 Clock..................................................................................................................... 350
13.4.4 SCI Initialization (Asynchronous Mode).............................................................. 351
13.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 352
13.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 354
13.5 Multiprocessor Communication Function.......................................................................... 358
13.5.1 Multiprocessor Serial Data Transmission ............................................................. 360
13.5.2 Multiprocessor Serial Data Reception .................................................................. 361
13.6 Operation in Clock Synchronous Mode............................................................................. 365
Rev. 1.00 Mar. 17, 2008 Page xvi of xl
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页数 | 30 页 | ||
下载 | [ R4F2164.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
R4F2164 | 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series | Renesas Technology |
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