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PDF ( 数据手册 , 数据表 ) UG-2864ASYDT03

零件编号 UG-2864ASYDT03
描述 OEL Display Module
制造商 Univision Technology
LOGO Univision Technology LOGO 


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UG-2864ASYDT03 数据手册, 描述, 功能
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Product Specification
Part Name: OEL Display Module
Part ID: UG-2864ASYDT03
Doc No.: SAS1-9031-B
Customer:
Approved by
From: Univision Technology Inc.
Approved by
Univision Technology Inc.
8, Kebei RD 2, Science Park, Chu-Nan, Taiwan 350, R.O.C.
Notes:
1. Please contact Univision Technology Inc. before assigning your product based on this
module specification
2. The information contained herein is presented merely to indicate the characteristics and
performance of our products. No responsibility is assumed by Univision Technology
Inc. for any intellectual property claims or other problems that may result from
application based on the module described herein.







UG-2864ASYDT03 pdf, 数据表
Univision Technology Inc.
1.5 Pin Definition
Doc. wNwo:wS.DAaSt1a-S9he0e3t14-UB.com
Pin Number Symbol
Power Supply
21 VDD
29 VSS
2
Driver
4
VCC
IREF
3 VCOMH
30
Interface
20
19
VSL
BS1
BS2
16 RES#
17 CS#
15 D/C#
I/O Function
Power Supply for Logic Circuit
P This is a voltage supply pin. It must be connected to
external source.
Ground of OEL System
P
This is a ground pin. It also acts as a reference for the
logic pins, the OEL driving voltages, and the analog
circuits. It must be connected to external ground.
Power Supply for OEL Panel
P This is the most positive voltage supply pin of the chip.
It must be supplied externally.
Current Reference for Brightness Adjustment
I
This pin is segment current reference pin. A resistor
should be connected between this pin and VSS. Set the
current at 10μA.
Voltage Output High Level for COM Signal
This pin is the input pin for the voltage output high level
P for COM signals. It can be supplied externally or
internally. When VCOMH is generated internally, a
capacitor should be connected between this pin and VSS.
Voltage Output Low Level for SEG Signal
O
This pin is the output pin for the voltage output low level
for SEG signals. A capacitor should be connected
between this pin and VSS.
Communicating Protocol Select
These pins are MCU interface selection input. See the
I
following table:
68XX-parallel 80XX-parallel
Serial
BS1 0
10
BS2 1
10
Power Reset for Controller and Driver
I This pin is reset signal input. When the pin is low,
initialization of the chip is executed.
Chip Select
I This pin is the chip select input. The chip is enabled for
MCU communication only when CS# is pulled low.
Data/Command Control
This pin is Data/Command control pin. When the pin is
pulled high, the input at D7~D0 is treated as display data.
When the pin is pulled low, the input at D7~D0 will be
transferred to the command register. For detail
I relationship to MCU interface signals, please refer to the
Timing Characteristics Diagrams.
When the pin is pulled high and serial interface mode is
selected, the data at SDIN is treated as data. When it is
pulled low, the data at SDIN will be transferred to the
command register.
3







UG-2864ASYDT03 equivalent, schematic
Univision Technology Inc.
4. Functional Specification
Doc. wNwo:wS.DAaSta1-S9he0e3t14-UB.com
4.1. Commands
Refer to the Technical Manual for the SSD1325
4.2 Power down and Power up Sequence
To protect OEL panel and extend the panel life time, the driver IC power up/down
routine should include a delay period between high voltage and low voltage power
sources during turn on/off. It gives the OEL panel enough time to complete the
action of charge and discharge before/after the operation.
4.2.1 Power up Sequence:
1. Power up VDD
2. Send Display off command
3. Initialization
4. Clear Screen
5. Power up VCC
6. Delay 100ms
(When VCC is stable)
7. Send Display on command
VCC
VDD
VSS/Ground
VDD on
VCC on
Display on
4.2.2 Power down Sequence:
1. Send Display off command
2. Power down VCC
3. Delay 100ms
(When VCC is reach 0 and panel
is completely discharges)
4. Power down VDD
VCC
VDD
VSS/Ground
Display off
VCC off
VDD off
4.3 Reset Circuit
When RES# input is low, the chip is initialized with the following status:
1. Display is OFF
2. 128×80 Display Mode
3. Normal segment and display data column and row address mapping (SEG0
mapped to column address 00h and COM0 mapped to row address 00h)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
6. Column address counter is set at 0
7. Normal scan direction of the COM outputs
8. Contrast control register is set at 80h
9. Normal display mode (Equivalent to A4h command)
11










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