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PDF ( 数据手册 , 数据表 ) GG1203N4SKY1B

零件编号 GG1203N4SKY1B
描述 Display
制造商 Solomon
LOGO Solomon LOGO 


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GG1203N4SKY1B 数据手册, 描述, 功能
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KAOHSIUNG FACTORY : NO. 18 Ta-Yeh St., Ta-Fa Industrial Park,Ta-Liao
Hsiang, Kaohsiung Hsien 831, TAIWAN , R.O.C.
TEL : 886-7-788-6800
FAX : 886-7-788-6806~8
PART NO : GG1203N4SKY1B(LM6480SGL)
FOR MESSRS :
CONTENTS
NO. ITEM
1. COVER
2. RECORD OF REVISION
3. GENERAL SPECIFICATIONS AND MECHANICAL DATA
4. ABSOLUTE MAXIMUM RATINGS
5. ELECTRICAL AND OPTICAL CHARACTERISTICS
6. OUTLINE DIMENSION AND TIMING CHARACTERISTICS
7. BLOCK DIAGRAM AND POWER SUPPLY
8. DISPLAY CONTROL INSTRUCTIONS
PAGE
1
2
3
4
5~7
8~10
11
12~26
Accepted by :
Proposed by :
Date : 09,11,2002
SOLOMON GOLDENTEK DISPLAY CORP.
TEL : 886-7-788-6800 FAX : 886-7-788-6806~8
GG1203N4SKY1B
REV : 8
PAGE : 1







GG1203N4SKY1B pdf, 数据表
6. OUTLINE DIMENSION
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NUIT : mm
SCALE : NTS
NON-SPECIFIED TOLERANCE ±0.3
INTERFACE PIN CONNECTION:
NO. 1 2 3 4 5 6 7 8 9 10
SYMBOL VSS VDD VO Vout A0 R/W E DB0 DB1 DB2
NO. 11 12 13 14 15 16 17 18 19 20
SYMBOL DB3 DB4 DB5 DB6 DB7 C86 CS1 CS2 LED(+) LED(-)
SOLOMON GOLDENTEK DISPLAY CORP.
TEL : 886-7-788-6800 FAX : 886-7-788-6806~8
GG1203N4SKY1B
REV : 8
PAGE : 8







GG1203N4SKY1B equivalent, schematic
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Note
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The 65 rows are divided into 8 pages of lines and a ninth page with a single line (D0 only ).
Data is read from or written to the 8 lines of each page directly through D0 to D7 . The time
taken to transfer data is very short , because the microprocessor inputs D0 toD7 correspond
to the LCD common line as show below .
D0 1
COM0
D1 0
COM1
D2 1
COM2
D3 0
COM3
D4 0
COM4
The microprocessor read from and write to RAM through the I/O buffer . Since
the LCD controller operates independently , data can be written to RAM at the
same time as being displayed , without causing the LCD to flicker .
Column Address Counter
The column address counter is an 8-bit presentable counter that provides the
column address to display data RAM . It is incremented by 1 each time a read or
write command is received . The counter automatically stops at the highest
address counter , A6H . The contents of the column address counter are changed
by the Column Address Set command . This counter is independent of the page
a address register .
When the select ADC command is used to select inverse display operation , The
column address decoder inverts the relationship between the RAM column data
and the display segment outputs .
Page Address Register
The 4-bit page address register provides the page address to display data RAM .
The contents of the register are changed by the Address Set command .
Page address 8(D3=H , D2 , D1, D0=L ) is a special use RAM area for the
indicate .
Initial Display Line Register
The initial display line register stores the address of the RAM line that
corresponds to the first (normally the top ) line ( com0 ) of the display . The
contents of this 6-bit register are changed by the initial display line command .
At the start of each LCD frame , synchronized with SYNC , the initial line is
copied to the line counter . the line counter is then incremented on the CL clock
signal once for every display line . this generates the line address for transfer of
the 166 bits of RAM data to the LCD drivers . If a 1/65 or 1/33 display duty
cycle is selected by the duty+1 command , the line address corresponding to the
65th or 33rd SYNC signal is changed and the indicator special-use line address
is selected . If the Duty+1
SOLOMON GOLDENTEK DISPLAY CORP.
TEL : 886-7-788-6800 FAX : 886-7-788-6806~8
GG1203N4SKY1B
REV : 8
PAGE : 16










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