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PDF ( 数据手册 , 数据表 ) LC78628

零件编号 LC78628
描述 Compact Disc Player DSP with Built-in HDCD Decoder
制造商 Sanyo Semicon Device
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LC78628 数据手册, 描述, 功能
Ordering number : ENN6329
CMOS IC
LC78628E
Compact Disc Player DSP with Built-in HDCD Decoder
®
Overview
The LC78628E CMOS IC implements signal processing
and servo control for compact disc players, laser disc
players, CD-V, CD-I, and similar products. It provides
functions for demodulation of the EFM signal from the
optical pickup, deinterleaving, error detection and
correction, and processing servo system commands issued
by the system microprocessor. In addition to this basic CD
functionality, it also provides HDCD (High Definition
Compatible Digital) decoding functions and CD text
functions. It also includes a built-in EFM PLL circuit.
Functions
• Full decoding and playback for discs encoded with the
HDCD technique developed by Pacific Microsonics,
Inc.
• Slices the high-frequency input signal at an accurate
level, converts it into the EFM signal, and generates a
PLL clock with an average frequency of 4.3218 MHz
performing a phase comparison with an internal VCO.
• Accurately generates a reference clock signal and all
necessary internal timings using an external 16.9344-
MHz crystal.
• Controls the disc motor speed using a frame phase
difference signal created based on the reproduced clock
signal and the reference clock.
• Performs detection, protection, and interpolation for the
frame synchronizing signal to assure stable data readout.
• Demodulates the EFM signal, converting it to 8-bit
symbol data.
• After applying a CRC check to the subcode Q signal,
outputs that data to the control microprocessor using
serial data transfer.
Package Dimensions
Continued on next page.
unit: mm
3174-QIP80E
0.8 0.8
64
65
[LC78628E]
23.2
20.0
0.35
1.6
41
40
0.15
80
1
25
24
2.7
21.6 0.8
SANYO: QIP80E
®
HDCD® (High Definition Compatible Digital®) is a registered trademark of Pacific Microsonics, Inc.
in the US and other countries.
A license from Pacific Microsonics, Inc. is required to use this product.
Sanyo Electric Co., Ltd. has acquired license for the use of HDCD technology from Pacific Microsonics, Inc.
The following patents apply to the design of this product:
USA: 5479168, 5638074, 5640161, 5808574, 5838274, 5854600, and 5872531.
Australia: 669114
Other patents have also been applied for.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
32400RM (OT) No. 6329-1/40







LC78628 pdf, 数据表
LC78628E
Reference Circuit for the 1-Bit D/A Converter Output Block
+
No. 6329-8/40







LC78628 equivalent, schematic
LC78628E
• Track jump commands
Code
$A0
$A1
$11
$12
$31
$52
$10
$13
$14
$30
$15
$17
$19
$1A
$39
$5A
$18
$1B
$1C
$38
$1D
$1F
$16
$0F
$8F
$8C
$21
$20
Command
Previous Track Jump Mode
New Track Jump Mode
1 TRACK JUMP IN #1
1 TRACK JUMP IN #2
1 TRACK JUMP IN #3
1 TRACK JUMP IN #4
2 TRACK JUMP IN
4 TRACK JUMP IN
16 TRACK JUMP IN
32 TRACK JUMP IN
64 TRACK JUMP IN
128 TRACK JUMP IN
1 TRACK JUMP OUT #1
1 TRACK JUMP OUT #2
1 TRACK JUMP OUT #3
1 TRACK JUMP OUT #4
2 TRACK JUMP OUT
4 TRACK JUMP OUT
16 TRACK JUMP OUT
32 TRACK JUMP OUT
64 TRACK JUMP OUT
128 TRACK JUMP OUT
256 TRACK CHECK
TOFF
TON
TRACK JUMP BRAKE
JP pulse period TOFF output mode
Reset the JP pulse period TOFF output mode
RES = low
q
q
q
JP–(+)
JP+(–)
(Braking period)
TGL
(JP pulse width)
ab
c
A12812
When the LC78628E receives a track jump instruction as a servo command, it first generates accelerating pulses (period
a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the specified
jump. During the braking period, the LC78628E detects the beam slip direction from the TES and HFL inputs. TOFF is
used to cut the components in the TES signal that aggravate slip. The jump destination track is captured by increasing the
servo gain with TGL. In JP pulse period TOFF output mode, TOFF goes high during the period that JP pulses are
generated.
Note: Of the modes related to disc motor control, the TOFF pin goes low only in CLV mode, and will be high during
start, stop, and brake operations. Note that the TOFF pin can be turned on and off independently by microprocessor
issued commands. However, this function is valid only when disc motor control is in CLV mode.
No. 6329-16/40










页数 30 页
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