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PDF ( 数据手册 , 数据表 ) LC78624E

零件编号 LC78624E
描述 Compact Disc Player DSP
制造商 Sanyo Semicon Device
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LC78624E 数据手册, 描述, 功能
Ordering number : EN5811
CMOS LSI
LC78624E
Compact Disc Player DSP
Overview
The LC78624E is a CMOS LSI that implements the signal
processing and servo control required by compact disc
players. Including an EFM-PLL and text decoder, the
LC78624E strictly limits functionality to basic signal
processing and servo system operation to achieve the best
cost-performance balance for low-end players. As basic
functions, the LC78624E provides demodulation of the
EFM signal from the optical pickup, de-interleaving, error
detection and correction, and processes servo commands
sent from the control microcontroller.
Functions
• Input signal processing: The LC78624E takes an HF
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
an internal VCO.
• Precise reference clock and necessary internal timing
generation using an external 16.9344 MHz crystal
oscillator
• Disk motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microcontroller
• Subcode Q signal output to a microcontroller over the
serial I/O interface after performing a CRC error check
(LSB first)
• Serial output to a microcontroller via the text decoder of
the song titles and other text data stored in the Subcode
R through W channels of the read-in area
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disk rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
• The LC78624E sets the C2 flags based on the C1 flags
and a C2 check, and then performs signal interpolation
or muting depending on the C2 flags. The interpolation
circuit uses a dual-interpolation scheme. The previous
value is held if the C2 flags indicate errors two or more
times consecutively.
• Support for command input from a microcontroller:
commands include track jump, focus start, disk motor
start/stop, muting on/off and track count (8 bit serial
input)
• Built-in digital output circuits.
• Arbitrary track counting to support high-speed data
access
• Zero cross muting
• Supports the implementation of a double-speed dubbing
function.
• Support for bilingual applications.
• General-purpose I/O ports: 5 pins
Features
• 64 pin QFP
• 5 V single-voltage power supply
Package Dimensions
unit: mm
3159-QFP64E
[LC78624E]
SANYO: QIP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
20698RM (OT) No. 5811-1/27







LC78624E pdf, 数据表
LC78624E
Continued from preceding page.
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
SBCK
FSX
WRQ
RWC
SQOUT
COIN
CQCK
RES
TST11
16M
4.2M
TEST5
CS
TEST1
I/O Function
I Subcode readout clock input. This is a Schmitt input. (Must be connected to 0 V when unused.)
O Output for the 7.35 kHz synchronization signal divided from the crystal oscillator
O Subcode Q output standby output
I Read/write control input. This is a Schmitt input.
O Subcode Q output
I Command input from the control microcontroller
I Input for both the command input clock and the subcode readout clock. This is a Schmitt input.
I Chip reset input. This pin must be set low briefly after power is first applied.
O Test output. Leave open. (Normally outputs a low level.)
O 16.9344 MHz output.
O 4.2336 MHz output
I Test input. A pull-down resistor is built in. Must be connected to 0 V.
I Chip select input. A pull-down resistor is built in. Must be connected to 0 V if not controlled.
I Test input. No pull-down resistor. Must be connected to 0 V.
Note: The same potential must be supplied to all power supply pins, i.e., VDD, VVDD and XVDD.
Pin Applications
1. HF Signal Input Circuit; Pin 10: EFMIN, pin 9: EFMO, pin 1: DEFI, pin 12: CLV+
An EFM signal (NRZ) sliced at an optimal level can be
acquired by inputting the HF signal to EFMIN.
The LC78624E handles defects as follows. When a high level is
input to the DEFI pin (pin 1), EFMO (pin 9) pins (the slice level
control outputs) go to the high-impedance state, and the slice
level is held. However, note that this function is only valid in
CLV phase control mode, that is, when the V/P pin (pin 14) is
low. This function can be used in combination with the
LA9230M, and LA9240M DEF pins.
A09900 Note: If the EFMIN and CLV+ signal lines are too close to
each other, unwanted radiation can result in error rate
degradation. We recommend laying a ground or VDD
shield line between these two lines.
2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK
Since the LC78624E includes a VCO circuit, a PLL circuit can
Frequency
phase
comparator
be formed by connecting external R and C (resistors and
capacitors). ISET is the charge pump reference current, PDO is
the VCO circuit loop filter, and FR is a resistor that determines
the VCO frequency range.
(Reference values)
R1 = 68 k, C1 = 0.1 µF
R2 = 680 , C2 = 0.1 µF
R3 = 1.2 k
A09901
Code
$AC
$AD
COMMAND
VCO × 2 SET
VCO × 1 SET
RES = low
q
The VCO × 2 command is an auxiliary command for characteristics guarantee in low-voltage operations. This
command supports the low-voltage operations at VDD = 3.0 to 3.6 V.
No. 5811-8/27







LC78624E equivalent, schematic
LC78624E
6. Tracking brake
The chart shows the relationships between the TES, HFL, and TOFF signals during the track jump C period. The TOFF signal is extracted from the
HFL signal by TES signal edges. When the HFL signal is high, the pickup is over the mirror surface, and when low, the pickup is over data bits.
Thus braking is applied based on the TOFF signal being high when the pickup is moving from a mirror region to a data region and being low when
the pickup is moving from a data region to a mirror region.
• JP three-value output
A09911
Code
$B6
$B7
Command
JP THREE-VALUE OUTPUT
JP TWO-VALUE OUTPUT (earlier scheme)
RES = low
q
The JP three-value output command allows the track jump operation to be controlled from a single pin.
Two-value
output
Three-value
output
A09912
• Track check mode
Code
$F0
$F8
$FF
Command
TRACK CHECK IN
TRACK CHECK OUT
TWO-BYTE COMMAND RESET
RES = low
q
The LC78624E will count the specified number of tracks plus one when the microcontroller sends an arbitrary
binary value in the range 8 to 254 after issuing either a track check in or a track check out command.
A09913
No. 5811-16/27










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