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PDF ( 数据手册 , 数据表 ) ORT42G5

零件编号 ORT42G5
描述 0.6 to 3.7 Gbps XAUI and FC FPSCs
制造商 Lattice Semiconductor
LOGO Lattice Semiconductor LOGO 


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ORT42G5 数据手册, 描述, 功能
ORCA® ORT42G5 and ORT82G5www.DataSheet4U.com
0.6 to 3.7 Gbps
XAUI and FC FPSCs
July 2008
Data Sheet DS1027
Introduction
Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane
data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the
ORT42G5 and ORT82G5 are made up of SERDES transceivers containing four and eight channels respectively.
Each channel operates at up to 3.7 Gbps across 26 inches of FR-4 backplane, with a full-duplex synchronous inter-
face with built-in Rx Clock and Data Recovery (CDR), and transmitter preemphasis, along with more than 400K
usable FPGA system gates. The CDR circuitry available from Lattice’s high-speed I/O portfolio (sysHSI™), has
already been proven in numerous applications, to create interfaces for SONET/SDH, Fibre Channel, and Ethernet
(GbE, 10 GbE) applications.
Designers can also use these devices to drive high-speed data transfer across buses within any generic system.
For example, designers can build a bridge for 10 G Ethernet: the high-speed SERDES interfaces can implement a
XAUI interface with a configurable back-end interface such as XGMII. The ORT42G5 and ORT82G5 can also be
used to provide a full 10 G backplane data connection and, in the case of the ORT82G5, provide both work and
protection links between a line card and switch fabric.
The ORT42G5 and ORT82G5 provide a clockless high-speed interface for interdevice communication on a board
or across a backplane. The built-in clock recovery of the ORT42G5 and ORT82G5 allows for higher system perfor-
mance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network
designers will benefit from the backplane transceiver as a network termination device. The device supports embed-
ded 8b/10b encoding/decoding and link state machines for 10 G Ethernet, and Fibre Channel.
The ORT82G5 is pinout compatible with a sister device, the ORSO82G5, which implements eight channels of
SERDES with SONET scrambling and cell processing. The ORT42G5 is pin compatible with the ORSO42G5,
which implements four channels of SERDES with SONET scrambling and cell processing.
Table 1. ORCA ORT42G5 and ORT82G5 Family – Available FPGA Logic
Device
PFU
FPGA Max.
PFU Rows Columns Total PFUs User I/O
LUTs
EBR EBR Bits2 FPGA System
Blocks2
(K)
Gates (K)1
ORT42G5
36
36
1296
204
10,368
12
111
333-643
ORT82G5
36
36
1296
372
10,368
12
111
333-643
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The system gate ranges
are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR
usage and two PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage
and four PLLs.
2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1027_07.0







ORT42G5 pdf, 数据表
Lattice Semiconductor
ORCA ORT42G5 and ORTw8w2wG.D5atDaSahteaetS4Uh.ceoemt
FPGA Logic Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It
includes enhancements and innovations geared toward today’s high-speed systems on a single chip. Designed
with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce
logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhance-
ments and are offered in a variety of packages and speed grades.
The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge
of FPGA and ASIC designs. Modular hardware and software technologies enable System-on-Chip integration with
true plug-and-play design implementation.
The architecture consists of four basic elements: Programmable Logic Cells (PLCs), Programmable I/O cells
(PIOs), Embedded Block RAMs (EBRs), plus supporting system-level features. These elements are interconnected
with a rich routing fabric of both global and local wires. An array of PLCs is surrounded by common interface blocks
which provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these crit-
ical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core.
Each PLC contains a PFU, SLIC, local routing resources, and configuration RAM. Most of the FPGA logic is per-
formed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs
provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output
multiplexing, uplink and downlink functions, and other functions on two output signals.
Large blocks of 512 x 18 block-port RAM complement the existing distributed PFU memory. The RAM blocks can
be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the
MPI, PLLs, and the Embedded System Bus (ESB).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional Flip-Flop that
may be used independently or with arithmetic functions.
The PFU is organized in a twin-block fashion; two sets of four LUTs and FFs that can be controlled independently.
Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may
also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The
carry-out of either mode may be registered in the ninth FF for pipelining.
Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The
FFs also have programmable clock polarity, clock enables, and local set/reset.
The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidi-
rectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional
INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU
outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for real-
world system performance.
Programmable I/O
The Series 4 PIO addresses the demand for the flexibility to select I/Os that meet system interface requirements.
I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features which
allow the user the flexibility to select new I/O types that support High-Speed Interfaces.
Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA
array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset,
and global set/reset. On the input side, each PIO contains a programmable latch/Flip-Flop which enables very fast
latching of data from any pad. The combination provides for very low setup requirements and zero hold times for
8







ORT42G5 equivalent, schematic
Lattice Semiconductor
ORCA ORT42G5 and ORTw8w2wG.D5atDaSahteaetS4Uh.ceoemt
Transmit Path (FPGA to Backplane) Logic
The transmitter section accepts four groups of either 8-bit unencoded data or 10-bit encoded data at the parallel
interface to the FPGA logic. It also uses the reference clock, REFCLK[P:N]_[A:B] to synthesize an internal high-
speed serial bit clock. The serialized transmitted data are available at the differential CML output pins to drive either
an optical transmitters, coaxial media or a circuit board backplane.
As shown in Figure 3, the basic blocks in the transmit path include:
Embedded Core/FPGA interface and 4:1 multiplexer
• Low speed parallel core/FPGA interface
• 4:1 multiplexer
Transmit SERDES
• 8b/10b Encoder
• 10:1 Multiplexer
• CML Output Buffer
Detailed descriptions of the logic blocks are given in following sections. Detailed descriptions of transmit clock dis-
tribution, including the transmit PLL are given in later sections of this data sheet.
Figure 3. Basic Logic Blocks, Transmit Path, Single Channel (Typical Reference Clock Frequency)
FPGA
Logic
TWDxx[31:0] 32
TCOMMAxx[3:0] 4
TBIT9xx[3:0] 4
TSYS_CLK_xx
For ORT42G5: xx = [AC, AD, BC or BD]
For ORT82G5: xx = [AA, AB, ... BD]
Interface and MUX Block
FIFO
4:1 MUX
(x9)
STBD_xx[7:0]
8-bit data 8
STBD_xx[8]
K-control
STBD_xx[9]
Force-ve disparity
TX SERDES Block
8B/10B
Encoder
(with
bypass)
10:1
MUX
CML
Buffer
with Pre-
emphasis
Backplane
Serial
Link
HDOUTP_xx
HDOUTN_xx
÷ 4 STBC311_xx PLL
312.5 MHz
TCK78[A:B]
78.125 MHz
Logic Common to Block
MUX
From other channel
or channels
{To other
channel or
channels
From Control
TCKSEL[0:1][A:B]
Register
CML
Buffer
REFCLKP_[A:B]
REFCLKN_[A:B]
156.25 MHz
16










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