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PDF ( 数据手册 , 数据表 ) LX128EC

零件编号 LX128EC
描述 High Performance Interfacing and Switching
制造商 Lattice Semiconductor
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LX128EC 数据手册, 描述, 功能
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ispGDX2Family
Includes
High-
High Performance Interfacing and Switching
September 2005
Features
Performance,
Low-Cost
“E-Series” Two Options Available
Data Sheet
• High-performance sysHSI (standard part number)
High Performance Bus Switching
• Low-cost, no sysHSI (“E-Series”)
• High bandwidth
– Up to 12.8 Gbps (SERDES)
sysHSI Blocks Provide up to 16 High-speed
– Up to 38 Gbps (without SERDES)
Channels
• Up to 16 (15x10) FIFOs for data buffering
• Serializer/de-serializer (SERDES) included
• High speed performance
• Clock Data Recovery (CDR) built in
– fMAX = 360MHz
– tPD = 3.0ns
– tCO = 2.9ns
– tS = 2.0ns
• Built-in programmable control logic capability
• 800 Mbps per channel
• LVDS differential support
• 10B/12B support
– Encoding / decoding
– Bit alignment
• I/O intensive: 64 to 256 I/Os
– Symbol alignment
• Expanded MUX capability up to 188:1 MUX
• 8B/10B support
– Bit alignment
sysCLOCK™ PLL
– Symbol alignment
• Frequency synthesis and skew management
• Source Synchronous support
• Clock multiply and divide capability
• Clock shifting up to +/-2.35ns in 335ps steps
Flexible Programming and Testing
• Up to four PLLs
• IEEE 1532 compliant In-System Programmabil-
ity (ISP™)
sysIO™ Interfacing
• Boundary scan test through IEEE 1149.1
• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
interface
standard board interfaces
• 3.3V, 2.5V or 1.8V power supplies
• SSTL 2/3 Class I and II support
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
• HSTL Class I, III and IV support
interfaces
• GTL+, PCI-X for bus interfaces
• LVPECL, LVDS and Bus LVDS differential support
• Hot socketing
• Programmable drive strength
Table 1. ispGDX2 Family Selection Guide
ispGDX2-64/E
ispGDX2-128/E
ispGDX2-256/E
I/Os 64 128 256
GDX Blocks
4 8 16
tPD
tS
tCO
fMAX (Toggle)
Max Bandwidth
sysHSI Channels2
SERDES1, 2
Without SERDES3
3.0ns
2.0ns
2.9ns
360MHz
3.2Gbps
11Gbps
4
3.2ns
2.0ns
3.1ns
330MHz
6.4Gbps
21Gbps
8
3.5ns
2.0ns
3.2ns
300MHz
12.8Gbps
38Gbps
16
LVDS/Bus LVDS (Pairs)
32 64 128
PLLs
224
Package
100-ball fpBGA
208-ball fpBGA
484-ball fpBGA
1. Max number of SERDES channels per device * 800Mbps
2. “E-Series” does not support sysHSI.
3. fMAX (Toggle) * maximum I/Os divided by 2.
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13







LX128EC pdf, 数据表
Lattice Semiconductor
Figure 5. ispGDX2-256 sysIO Banks
ispGDX2 Fwawmwi.lDyatDaSahteaetS4Uh.ceoemt
VCCO5
VREF5
GND
VCCO6
VREF6
GND
sysIO Bank 4
sysIO Bank 5
sysIO Bank 3
sysIO Bank 2
sysIO Bank 6
sysIO Bank 7
sysIO Bank 1
sysIO Bank 0
VCCO2
VREF2
GND
VCCO1
VREF1
GND
There are three classes of I/O interface standards implemented in the ispGDX2 devices. The first is the non-termi-
nated, single-ended interface; it includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V LVCMOS
interface standards. The slew rate and strength of these output buffers can be controlled individually. Additionally,
PCI 3.3, PCI-X and AGP-1X are all subsets of this interface type. The second interface class implemented is the
terminated, single-ended interface standard. This group of interfaces includes different versions of SSTL and HSTL
interfaces along with CTT and GTL+. Use of these I/O interfaces requires an additional VREF signal. At the system
level, a termination voltage, VTT, is also required. Typically, an output will be terminated to VTT at the receiving end
of the transmission line it is driving. The final types of interfaces implemented are the differential standards
LVPECL, LVDS and Bus LVDS. Table 3 shows the I/O standards supported by the ispGDX2 devices along with
nominal VCCO, VREF and VTT.
The ispGDX2 family also features 5V tolerant I/O. I/O banks with VCCO = 3.3V may have inputs driven to a maxi-
mum of 5.5V for easy interfacing with legacy systems. Up to 64 I/O pins per device may be driven by 5V inputs.
8







LX128EC equivalent, schematic
Lattice Semiconductor
Figure 13. Operation in FIFO Mode2
GRP
GDX Block 1
FIFO
ispGDX2 Fwawmwi.lDyatDaSahteaetS4Uh.ceoemt
SERDES
Pre-Assigned Pins
Input
Reg/
Latch
Output
Reg/
Latch
Input
Reg/
Latch
Delay
10
DOUT
RCLK
RE
10
DIN
RXD
Parallel
Data
Serial
Data In
(SIN)
10
PT-CLK/CE(0:3)
TXD Serial
Parallel Data Out
Data (SOUT)
WE
GCLK/CE(0:3)
WCLK
RECCLK
Input
Reg/
Latch
Output
Reg/
Latch
FULL
EMPTY
Output
Reg/
Latch
FIFORSTb
Notes:
1. For clarity, only a portion of the GDX Block is shown.
2. Some signals share pins. See Logic Signal Connections tables for details.
SYDT
CDRRSTb
POR
RESETb
CAL
16










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