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零件编号 | AD6636 | ||
描述 | 150 MSPS Wideband Digital Down-Converter (DDC) | ||
制造商 | Analog Devices | ||
LOGO | |||
1 Page
150 MSPS Wideband
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Digital Down-Converter (DDC)
AD6636
FEATURES
4/6 independent wideband processing channels
Processes 6 wideband carriers (UMTS, CDMA2000)
4 single-ended or 2 LVDS parallel input ports
(16 linear bit plus 3-bit exponent) running at 150 MHz
Supports 300 MSPS input using external interface logic
3 16-bit parallel output ports operating up to 200 MHz
Real or complex input ports
Quadrature correction and dc correction for complex inputs
Supports output rate up to 34 MSPS per channel
RMS/peak power monitoring of input ports
Programmable attenuator control for external gain ranging
3 programmable coefficient FIR filters per channel
2 decimating half-band filters per channel
6 programmable digital AGC loops with 96 dB range
Synchronous serial I/O operation (SPI®-, SPORT-compatible)
Supports 8-bit or 16-bit microport modes
3.3 V I/O, 1.8 V CMOS core
User-configurable built-in self-test (BIST) capability
JTAG boundary scan
APPLICATIONS
Multicarrier, multimode digital receivers
GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA
Micro and pico cell systems, software radios
Broadband data applications
Instrumentation and test equipment
Wireless local loop
In-building wireless telephony
FUNCTIONAL BLOCK DIAGRAM
CLKA
ADC A/AI
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
EXPA [2:0]
CLKB
ADC B/AQ
EXPB [2:0]
CLKC
ADC C/CI
CMOS
REAL
PORTS
A, B,
C,D
CMOS
EXPC [2:0] COMPLEX
PORTS
(AI, AQ)
CLKD (BI, BQ)
ADC D/CQ
EXPD [2:0]
______
RESET
SYNC [3:0]
LVDS
PORTS
AB, CD
PEAK/
RMS
MEAS.
I,Q
CORR.
NCO
NCO
NCO
NCO
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
PA
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
AGC PB
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
PC
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
PLL CLOCK
MULTIPLIER
16-BIT
MICROPORT INTERFACE
SPORT/SPI INTERFACE
JTAG
NOTE: CHANNELS RENDERED AS
ARE AVAILABLE ONLY IN 6-CHANNEL PART
M = DECIMATION
L = INTERPOLATION
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD6636
SERIAL PORT TIMING CHARACTERISTICS
Table 5. Serial Port Timing Characteristics1, 2
Parameter
SERIAL PORT CLOCK TIMING REQUIREMENTS
tSCLK
tSCLKL
tSCLKH
SCLK Period
SCLK Low Time
SCLK High Time
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0)
tSSI SDI to ↓SCLK Setup Time
tHSI SDI to ↓SCLK Hold Time
tSSCS SCS to ↑SCLK Setup Time
tHSCS SCS to ↑SCLK Hold Time
tDSDO
↑SCLK to SDO Delay Time
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1)
tSSI SDI to ↓SCLK Setup Time
tHSI SDI to ↓SCLK Hold Time
tSSRFS
SRFS to ↓SCLK Setup Time
tHSRFS
SRFS to ↓SCLK Hold Time
tSSTFS
STFS to ↑SCLK Setup Time
tHSTFS
STFS to ↑SCLK Hold Time
tSSCS SCS to ↑SCLK Setup Time
tHSCS SCS to ↑SCLK Hold Time
tDSDO
↑SCLK to SDO Delay Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
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Min Typ
Max Unit
10.0
1.60
0.5 × tSCLK
1.60
0.5 × tSCLK
ns
ns
ns
1.30
0.40
4.12
−2.78
4.28
ns
ns
ns
ns
7.96 ns
0.80
0.40
1.60
−0.13
1.60
−0.30
4.12
−2.76
4.29
ns
ns
ns
ns
ns
ns
ns
ns
7.95 ns
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
EXPLANATION OF TEST LEVELS FOR SPECIFICATIONS
I 100% production tested.
II 100% production tested at 25°C, and sample tested at specified temperatures.
III Sample tested only.
IV Parameter guaranteed by design and analysis.
V Parameter is typical value only.
VI 100% production tested at 25°C, and sampled tested at temperature extremes.
Rev. 0 | Page 8 of 72
AD6636
CPUCLK
RD
tSC
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tHC
WR
CS
A [7:0]
tSC
tSAM
D [15:0]
VALID ADDRESS
tHC
tHAM
tDD
VALID DATA
tDRDY
RDY
tACC
NOTE:
tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES.
Figure 14. INM Microport Read Timing Requirements
CPUCLK
tSC
DS
tHC
R/W
tSC
tHC
tSC
CS
tHC
A [7:0]
tSAM
VALID ADDRESS
tHAM
D [15:0]
tSAM
VALID DATA
tHAM
tDDTACK
DTACK
tACC
NOTE:
tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES.
Figure 15. MNM Microport Write Timing Requirements
Rev. 0 | Page 16 of 72
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页数 | 30 页 | ||
下载 | [ AD6636.PDF 数据手册 ] |
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