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PDF ( 数据手册 , 数据表 ) ADM1073

零件编号 ADM1073
描述 Full-Feature 48 V Hot Swap Controller
制造商 Analog Devices
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ADM1073 数据手册, 描述, 功能
Data Sheet
Full-Feature −48 V Hot Swap Controller
ADM1073
FEATURES
Precision inrush linear current limit
Soft start inrush current limit profiling
Precision maximum on-time in current limit
Maximum on-time modulated by FET drain voltage for
additional SOA protection
Adjustable PWM retry scheme and multiple device cascading
capability for charging large capacitive loads
Limited number of PWM cycles for FET SOA protection under
short circuit condition
Ability to configure device as continuous autoretry with a
5-second cooling period
Shunt regulator topology to allow very large transient input
supplies
Separate UV and OV pins for programming allowable input
supply window
Programmable OV hysteresis using current source into pin
when supply is high
Programmable UV hysteresis using current sink from pin
when supply is low
PWRGD output indicates when capacitor charging complete
SPLYGD output indicates when supply is within
valid window
LATCHED output indicates the end of the retry cycle before
load capacitance is charged
SHDN input for user-commanded shutdown
RESTART input for user-triggered 5-second shutdown and
autorestart— virtual card reseat
FUNCTIONAL BLOCK DIAGRAM
OV
UV
SS
TIMER
VIN
VCC AND
REFERENCE
GENERATOR
OVERVOLTAGE
DETECTOR
UNDERVOLTAGE
DETECTOR
SOFT START
CONTROL
tON CONTROL
5 SECOND
SHUTDOWN
SPLYGD
FOLDBACK
AND PWRGD
PWRGD
DRAIN
VIN
100mV(MAX)
50A
GATE
FAULT TIMER
AND CONTROL
OSCILLATOR PWM
TIMEOUT
SENSE
VEE
SHDN
RESTART
LATCHED
Figure 1.
APPLICATIONS
Central office switching
Telecommunication and data communication equipment
−48 V distributed power systems
Negative power supply control
High availability servers
−48 V power supply modules
Disk arrays
GENERAL DESCRIPTION
The ADM1073 is a full-feature, negative voltage, hot swap
controller that allows boards to be safely inserted and removed
from a live −48 V backplane. The part provides precise and
robust current limiting, and protection against both transient
and nontransient short circuits in overvoltage and undervoltage
conditions. The ADM1073 can operate from a negative voltage
of −18 V to −80 V and can tolerate transient voltages of up to
−200 V.
Inrush current is limited to a programmable value by control-
ling the gate drive of an external N-channel FET. The maximum
current limit is set by the choice of the sense resistor, RSENSE.
A built-in soft start function allows control of the inrush
current profile by an external capacitor on the soft start (SS)
pin.
An external capacitor on the TIMER pin determines the time
for which the FET gate is controlled to be high when maximum
inrush current flows. The ADM1073 employs a limited consec-
utive retry scheme, whereby, if the load capacitance is not fully
charged within one attempt, the FET gate is pulled low and
retries after a cooling period.
(continued on Page 3)
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADM1073 pdf, 数据表
Data Sheet
ADM1073
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESTART 1
14 SHDN
VIN 2
13 TIMER
PWRGD 3 ADM1073 12 UV
SS 4 TOP VIEW 11 OV
SENSE 5 (Not to Scale) 10 DRAIN
VEE 6
LATCHED 7
9 GATE
8 SPLYGD
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin Number Mnemonic
Function
1
RESTART
Input Pin. Edge-triggered 5-second shutdown and automatic restart.
2 VIN
Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via shunt resistor. A 1 µF
capacitor to VEE is recommended on the VIN pin.
3
PWRGD
Open Drain Output. Signals that the hot swap is complete.
4 SS
Analog Pin for Soft Start. An external capacitor on this pin sets the ramp rate of the inrush current
profile. This pin can be overdriven to alter the current limit control loop threshold.
5 SENSE
Voltage Input from External Sense Resistor.
6 VEE
Ground Supply to Chip (usually a −48 V system supply). Also low-side sense resistor connection.
7
LATCHED
Open Drain Output. Signals the end of the PWM retry period after a current fault.
8
SPLYGD
Open Drain Output. Signals that the device is not in reset and that the supply is in operating voltage
window.
9 GATE
Output to External FET Gate Drive.
10 DRAIN
Analog Input for Monitoring of FET Drain Voltage.
11 OV
Input Pin for Overvoltage Detection Circuitry.
12 UV
Input Pin for Undervoltage Detection Circuitry.
13 TIMER
Analog Pin. An external capacitor on this pin sets the maximum allowable time in current limit, the
PWM on-time, and the PWM duty cycle.
14 SHDN
Input Pin. Level-triggered device shutdown and reset.
Rev. B | Page 7 of 24







ADM1073 equivalent, schematic
Data Sheet
ADM1073
SENSE
The SENSE pin is used for sensing the voltage across an
external power sense resistor. This voltage is differentially
measured with respect to VEE, and used to control the GATE.
If SENSE is lower than 100 mV (after the soft start time), the
GATE pin is allowed to increase up to 12 V to provide
maximum FET enhancement. If the current increases such that
the SENSE pin tries to go above 100 mV, the GATE pin is
controlled in a feedback loop to ensure that the voltage across
the sense resistor is regulated at exactly 100 mV.
SENSE RESISTOR
The ADM1073’s current limiting function can operate at
different current levels. The current limit is determined by
selection of the sense resistor, RSENSE. Table 4 shows how the
maximum allowable load current (ILOAD(MAX)) and the minimum
and maximum inrush currents (ILIMIT(MIN) and I )LIMIT(MAX) are
related to the value of RSENSE.
Table 4. Minumum and Maximum Inrush Current and Load
Current Levels for Different Values of RSENSE
RSENSE (mΩ)
ILOAD(MAX) (A)
ILIMIT(MIN) (A) ILIMIT(MAX) (A)
5
17.20
19.40
20.60
10 8.60 9.70 10.30
15 5.73 6.47 6.87
18 4.78 5.39 5.72
22 3.91 4.41 4.68
33 2.61 2.94 3.12
47 1.83 2.06 2.19
51 1.69 1.90 2.02
68 1.26 1.43 1.51
75 1.15 1.29 1.37
90 0.96 1.08 1.14
SOFT START (SS PIN)
The SS pin is used to determine the inrush current profile.
A capacitor should be attached to this pin. Whenever the FET
is requested to turn on, the SS pin is held at ground until the
SENSE pin reaches a few mV. A current source is then turned
on, which linearly ramps the capacitor up to 2.5 V. The
reference voltage for the GATE linear control amplifier is
derived from the soft start voltage, such that the inrush linear
current limit is defined as
I LIMIT = VSOFT _ START / 20 × RSENSE
Overdriving the SS Pin
The SS pin can be overdriven externally from 0.360 V to 1.95 V
to offset the current limit control loop threshold from 18 mV to
100 mV. This allows different current limits to be selected at
different points of operation without using multiple sense
resistors. The current limit voltage is clamped at 100 mV
maximum.
GATE
Analog output for driving the external FET gate. This pin is
switched to VEE when the FET is off, is linearly controlled when
the FET is at the programmed inrush current limit, and is
switched to VIN when the FET is fully enhanced. The source
current capability is small to provide slow controlled turn-on,
and the sink current capability is large to provide fast turn-off.
VIN
Positive supply pin. This current-driven supply is shunt-
regulated at 12.3 V internally, and should be connected to the
most positive input supply terminal (usually −48 V RTN or 0 V)
through a dropper resistor. The resistor should be chosen such
that it always supplies enough current to overcome the
maximum quiescent supply current of the chip. Default RDROP =
30 kΩ.
VEE
Negative supply input. This pin should be connected directly to
the most negative input supply terminal (−48 V). This pin is
also used for differentially sensing across the external power
resistor, and should, therefore, be connected as close to the
sense resistor as possible. (See the Kelvin Sense Resistor
Connection section.)
TIMING CONTROL—TIMER
The TIMER pin is an analog pin that determines the maximum
on-time when the FET is in linear current limit, and controls
the PWM duty cycle for pulsed load capacitor charging. A
capacitor should be attached to this pin. When the FET is in
current limit, a 19 µA current source charges the external
capacitor. If the FET is still in current limit when the TIMER
capacitor reaches 2.5 V, the GATE driver is turned off and a
1 µA discharge current sink is turned on. The GATE remains
low until the TIMER capacitor is reduced to 0.5 V. At this point,
the GATE pin is turned on again. If the FET goes back into
current limit, the TIMER recharging starts again.
The PWM duty cycle is set at 6% default level by the size of
these two current sources. Adding a resistor from TIMER to VEE
decreases the duty cycle. Adding a resistor from TIMER to VIN
increases the duty cycle.
In addition, a current proportional to the current into the
DRAIN pin is added to the charging current. The additional
current varies linearly with DRAIN voltage. This reduces the
maximum on-time and the percentage PWM duty cycle when
there is a large voltage across the FET.
Rev. B | Page 15 of 24










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