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PDF ( 数据手册 , 数据表 ) WED3C755E8M-XBX

零件编号 WED3C755E8M-XBX
描述 RISC MICROPROCESSOR MULTI-CHIP PACKAGE
制造商 White Electronic Designs Corporation
LOGO White Electronic Designs Corporation LOGO 


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WED3C755E8M-XBX 数据手册, 描述, 功能
White Electronic Designs
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WED3C755E8M-XBX
RISC MICROPROCESSOR MULTI-CHIP PACKAGE
OVERVIEW
The WEDC 755E/SSRAM multichip package is targeted
for high performance, space sensitive, low power systems
and supports the following power management features:
doze, nap, sleep and dynamic power management. The
WED3C755E8M-XBX multichip package consists of:
755 RISC processor (E die revision)
Dedicated 1MB SSRAM L2 cache, configured as
128Kx72
21mmx25mm, 255 Ceramic Ball Grid Array (CBGA)
Core Frequency/L2 Cache Frequency (300MHz/
150MHz, 350MHz/175MHz)
Maximum 60x Bus frequency = 66MHz
FEATURES
The WED3C755E8M-XBX is offered in Commercial
(0°C to +70°C), industrial (-40°C to +85°C) and military
(-55°C to +125°C) temperature ranges and is well suited
for embedded applications such as missiles, aerospace,
flight computers, fire control systems and rugged critical
systems.
Footprint compatible with WED3C7558M-XBX and
WED3C750A8M-200BX
Footprint compatible with Motorola MPC 745
This product is subject to change without notice.
FIG. 1 - MULTI-CHIP PACKAGE DIAGRAM
µP
755E
SSRAM
SSRAM
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May, 2003
Rev 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com







WED3C755E8M-XBX pdf, 数据表
White Electronic Designs
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WED3C755E8M-XBX
POWER CONSUMTION
VCC=AVCC=2.0±0.1V, OVCC=3.3V ±5% VDC, GND=0 VDC, 0≤Tj<105°C
Full-on Mode
Typical
Maximum
Doze Mode
Maximum
Nap Mode
Maximum
Sleep Mode
Maximum
Sleep Mode–PLL and DLL Disabled
Maximum
NOTES:
1. These values apply for all valid 60x bus and L2 bus ratios. The values do
not include OVCC; AVCC and L2AVCC suppling power. OVCC power is system
dependent, but is typically <10% of VCC power. Worst case power consumption,
for AVCC=15mW and L2AVCC=15mW.
2. Maximum power is measured at VCC=2.1V while running an entirely cache-
resident, contrived sequence of instructions which keep the execution units
maximally busy.
Processor (CPU) Frequency/L2 Fre-
quency
Unit Notes
300/150 MHz
350/175MHz
4.1 4.6 W 1, 3
6.7 7.9 W 1, 2
2.5 2.8 W 1, 2
1700
1800
mW 1, 2
1200
1300
mW 1, 2
500 500 mW 1, 2
3. Typical power is an average value measured at VCC=AVCC=L2AVCC=2.0V,
OVCC=L2OVCC=3.3V in a system, executing typical applications and benchmark
sequences.
BGA THERMAL RESISTANCE
Description
Symbol
PPC
SSRAM
Junction to Ambient (No Airflow)
Theta JA
14.2
11.2
Junction to Ball
Theta JB
8.6
5.7
Junction to Case (Top)
Theta JC
0.1
0.1
NOTE 1: Refer to PBGA Thermal Resistance Correlation at www.whiteedc.com in the application notes section for modeling conditions
Units
C/W
C/W
C/W
Notes
1
1
1
L2 CACHE CONTROL REGISTER (L2CR)
The L2 cache control register, shown in Figure 5, is a supervisor-level, implementation-specific SPR used to configure
and operate the L2 cache. It is cleared by hard reset or power-on reset.
FIG. 5 - L2 CACHE CONTROL REGISTER (L2CR)
L2E L2PE L2SIZ L2CLK L2RAM L2DO L2I L2CTL L2WT L2TS L20H L2SL L2DF L2BYP 0
0 L2IO L2CS L2DRO
L2CTR
0 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
The L2CR bits are described in Table 1.
L2IP
30 31
Reserved
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May, 2003
Rev 2
8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com














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