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PDF ( 数据手册 , 数据表 ) LP1072

零件编号 LP1072
描述 802.11a/b/g Baseband System Solution
制造商 Freescale Semiconductor
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LP1072 数据手册, 描述, 功能
Freescale Semiconductor
Advance Information
Document Number: LP1072
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LP1072
802.11a/b/g Baseband System
Solution
1 Introduction
1.1 The LP1070 Family
Freescale Semiconductor’s 802.11 LP1070 family
consists of high-performance, highly optimized PHY
and MAC baseband Wireless LAN processors that fully
implement the IEEE 802.11a, 802.11b and 802.11g PHY
standards. These baseband processors are poised to
revolutionize the Wireless LAN industry by setting new
standards for power consumption, size, cost and
performance.
The LP1070 family is based on Freescale's proprietary
Wireless Broadband Signal Processor™ (WBSP™), an
innovative and revolutionary receiver architecture that
significantly reduces size and power consumption while
providing maximum flexibility to support multiple
wireless standards with no additional overhead.
In addition to their superior performance and ultra low
power consumption, the LP1070 processors provide the
customers with the flexibility to tailor the chip
characteristics to their needs. With software control, the
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Functional Description . . . . . . . . . . . . . . . . . 4
4 LP1072 Interfaces . . . . . . . . . . . . . . . . . . . . . 10
5 Timers/Reset . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Pinout and Footprint . . . . . . . . . . . . . . . . . . 17
7 DC Electrical Specifications . . . . . . . . . . . . 24
8 Timing Characteristics . . . . . . . . . . . . . . . . . 26
9 Mechanical Dimensions . . . . . . . . . . . . . . . . 29
10 Development Support . . . . . . . . . . . . . . . . . 29
11 Appendix: Comparison of LP1071 and
LP1072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12 Revision History . . . . . . . . . . . . . . . . . . . . . 31
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
PRELIMINARY







LP1072 pdf, 数据表
Functional Description
Parameter
Wake-up time
Table 3. I/Q ADC Specifications (continued)
Condition
From Shutdown
From Standby
Min Typ
——
——
3.4.2 I/Q DAC
I/Q DAC specifications are shown in Table 4.
Table 4. I/Q DAC
Parameter
Condition
Min
Resolution
——
Maximum Update rate
— 44
3dB Signal Bandwidth
——
Output common-mode voltage — 0.7
Load
— 10
——
Integral Nonlinearity (INL)
——
Differential Nonlinearity (DNL) — —
Total Harmonic Distortion (THD) Fin= 1MHz
Fin= 10MHz
SNR
Fin= 1MHz
Fin= 10MHz
ENOB
Fin= 1MHz
Fin= 10MHz
Channel-to-Channel mismatch Gain
Phase
DC offset after calibration
— -1
Wake-up time
From Shutdown
From Standby
1 See Analog input pin for definition of I/Q DAC output common-mode level.
Typ
8
11
Vcmo1
±1.0
± 0.5
-48.5
-47
48.5
47
7.2
7.0
0.2
0.5
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Max Units
1 ms
10 µs
Max Units
— bit
— MHz
— MHz
1.5 V
— Kohm
5 pF
— LSB
— LSB
— dB
— dB
— dB
— dB
— bit
— bit
— dB
— Degree
+1 LSB
10 µs
2 µs
LP1072 Advance Information, Rev. 0.3
8 Freescale Semiconductor
PRELIMINARY







LP1072 equivalent, schematic
Timers/Reset
5 Timers/Reset
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The TCXO generates the 40MHz RFIC 800 mV clipped sine wave reference clock.
The TCXO output is converted to a digital signal via a clock squarer input pad circuit. The 40 MHz TCXO
reference is used to generate the 40 MHz IQDAC clock and the 20 MHz IQADC clock. The PLL
synthesizes a reference from the 40 MHz reference. The reference is then used to generate the BRC, ARM,
PAS and Symbol Processor clocks, the 44 MHz IQ DAC clock and the 22 MHz IQ ADC clock. When the
TCXO and PLL are powered down the only active clock source is the 32 kHz XTAL, a.k.a. the Slow Clock.
The TCXO, PLL and XTAL clock references all include bypass MUXes which allow the individual clock
reference to be driven by an external signal.
Figure 3 illustrates the high level clocking of the LP1072 with the associated pins.
Chip
Boundary
PLL_BYPAS
S
PLL_BYPASS_CLK
TCXO_BYPASS
TCXO_BYPASS_CLK
TCXO 40 MHz
FAST_CLK_PWR
XTAL_BYPASS
XTAL_BYPASS_CLK
XTAL 32 kHz
PLL
40 MHz
88 MHz
Clock
Control
Cuircuits
44 MHz
20 MHz
22 MHz
ARM
AFE
32 kHz
Figure 3. LP1072 Clocks
5.1 System Clock
The LP1072 is clocked using an external crystal oscillator (XO) or a temperature compensated crystal
oscillator (TCXO) running at 40MHz with a frequency resolution of ± 20 ppm or better.
5.2 PLL Block
PLL Bypass
5.3 Low Frequency Clock
The LP1072 uses a low power 32 kHz crystal oscillator to maintain the timing during sleep.
LP1072 Advance Information, Rev. 0.3
16 Freescale Semiconductor
PRELIMINARY










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