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PDF ( 数据手册 , 数据表 ) ZL2005P

零件编号 ZL2005P
描述 Digital-DC Controller
制造商 Intersil Corporation
LOGO Intersil Corporation LOGO 


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ZL2005P 数据手册, 描述, 功能
Data Sheet
ZL2005P
www.DataSheet4U.com
February 18, 2009
FN6849.0
Digital-DC™ Controller with Drivers and POLA/DOSA Trim
Description
The ZL2005P is an innovative mixed-signal power
conversion and management IC that combines a com-
pact, efficient, synchronous DC-DC buck controller,
adaptive drivers and key power and thermal manage-
ment functions in one IC, providing flexibility and
scalability while decreasing board space requirements
and design complexity. Zilker Labs Digital-DC tech-
nology enables a unique blend of performance and
features not available in either traditional analog or
newer digital approaches, resolving the issues associ-
ated with providing multiple low-voltage power
domains on a single PCB.
The ZL2005P is designed to be configured either as a
standard ZL2005 or as POLA/DOSA compatible
device.
All operating features can be configured by simple
pin-strap selection, resistor selection or through the
on-board serial port. The PMBus™-compliant
ZL2005P uses the SMBus™ serial interface for com-
munication with other Digital-DC products or a host
controller.
Features Power Conversion
• Efficient synchronous buck controller
• 3 V to 14 V input range
• 0.54 V to 5.5 V output range (with margin)
• Optional output voltage setting with VADJ pin
• ± 1% output accuracy
• Internal 3 A drivers support >40 A power stage
• Fast load transient response
• Phase interleaving
• RoHS compliant (6 x 6 mm) QFN package
Power Management
• Digital soft start/stop
• Precision delay and ramp-up
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• I2C/SMBus communication
• Output overvoltage and overcurrent protection
• Internal non-voltatile memory (NVM)
• PMBus compliant
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
DLY FC ILIM
EN PG (0,1) (0,1) (0,1) CFG UVLO V25 VR VDD
SS (0,1)
VTRK
MGN
SYNC
VADJ
SCL
SDA
SALRT
POWER
MANAGEMENT
LDO
NON-
VOLATILE
MEMORY
I2C
DRIVER
PWM
CONTROLLER
MONITOR
ADC
CURRENT
SENSE
TEMP
SENSOR
BST
GH
SW
GL
ISENA
ISENB
SA (0,1)
XTEMP VSEN
PGND SGND DGND
Figure 1. Block Diagram
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







ZL2005P pdf, 数据表
ZL2005P
Table 4. Pin Descriptions (Continued)
www.DataSheet4U.com
Pin Label Type1
Description
18 VSEN
I Output voltage feedback. Connect to output regulation point.
19 ISENB
I Differential voltage input for current limit.
20 ISENA
I Differential voltage input for current limit. High voltage tolerant.
21 VR PWR Internal 5V reference used to power internal drivers.
22 GL
O Low side FET gate drive.
23 PGND PWR Power ground. Connect to low impedance ground plane.
24 SW PWR Drive train switch node.
25 GH
O High-side FET gate drive.
26 BST PWR High-side drive boost voltage.
27 VDD3 PWR Supply voltage.
28 V25 PWR Internal 2.5 V reference used to power internal circuitry.
29 XTEMP
I
External temperature sensor input. Connect to external 2N3904 diode connected
transistor.
30 VADJ
I Output voltage setting pin (POLA/DOSA mapping)
31 MGN
32 CFG
I Digital VOUT margin control
I
Configuration pin. Used to control the switching phase offset, sequencing and
other management features.
33 EN
I Enable. Active signal enables PWM switching.
34 DLY0
35 DLY1
I, M
Softstart delay select. Sets the delay from when EN is asserted until the output
voltage starts to ramp.
36 PG
O Power good output.
ePad SGND
PWR
Exposed thermal pad. Connect to low impedance ground plane. Internal
connection to SGND.
NOTES:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pin (refer to Section 4.5, “Multi-mode Pins,” )
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. VDD is measured internally and the value is used to modify the PWM loop gain.
8 FN6849.0
February 18, 2009







ZL2005P equivalent, schematic
ZL2005P
Table 8. Resistors for Setting POLA Output
Voltage with VADJ
VOUT
0.7V
RSET
in series with
10kΩ resistor
162 kΩ
VOUT
0.991V
RSET
in series with
10kΩ resistor
21.5 kΩ
0.752V 110 kΩ
1.00V 19.6 kΩ
0.758V 100 kΩ
1.10V 16.2 kΩ
0.765V 90.9 kΩ
1.158V 13.3 kΩ
0.772V 82.5 kΩ
1.200V 12.1 kΩ
0.79V 75.0 kΩ
1.25V 9.09 kΩ
0.80V 56.2 kΩ
1.50V 7.50 kΩ
0.821V 51.1 kΩ
1.669V 5.62 kΩ
0.834V 46.4 kΩ
1.80V 4.64 kΩ
0.848V 42.2 kΩ
2.295V 2.87 kΩ
0.880V 34.8 kΩ
2.506V 2.37 kΩ
0.899V 31.6 kΩ
3.30V 1.21 kΩ
0.919V 28.7 kΩ
5.00V 0.162 kΩ
0.965V 23.7 kΩ
The standard method for adjusting output voltage used
in POLA, is defined by the following equation:
Rset = 10kΩ x 0.69V/(VOUT – 0.69V) – 1.43kΩ
Rset is an external resistor.
0.69V
POLA Module
+
-
1.43
kOhm
RSET
10
kOhm
VOUT MODULE
ZL2005P
VADJ
10
kOhm
RSET
Figure 11. Output Voltage Resistor Setting
POLA - ZL2005P
To stay compatible with existing methods for adjusting
output voltage and to keep the same external Rset
resistor, the module manufacturer can add a 10 kΩ
resistor on the module.
RVADJ = RSET +10 kΩ
By adding this additional resistor, now the same resis-
tor used to set an output voltage with the analog POLA
method will provide the same owuwtpwu.Dt avtoalSthaegeet4wU.icthomthe
ZL2005P.
DOSA Voltage Trim Method
For DOSA output voltage selection, a 8.66 kΩ resistor
needs to be used in place of the 10 kΩ resistor. This
will allow setting the output voltage according to
DOSA equation:
Rset = 6900/(VOUT – 0.69V).
Table 9. Resistors for Setting DOSA Output
Voltage with VADJ
VOUT
0.7V
0.752V
0.758V
0.765V
0.772V
0.79V
0.80V
0.821V
0.834V
Rset
in series with
8.66kΩ
resistor
162 kΩ
113 kΩ
100 kΩ
90.9 kΩ
82.5 kΩ
75.0 kΩ
57.6kΩ
52.3 kΩ
47.5 kΩ
VOUT
0.991V
1.00V
1.10V
1.158V
1.200V
1.25V
1.50V
1.669V
1.80V
Rset
in series with
8.66kΩ
resistor
22.6 kΩ
21.0 kΩ
17.8 kΩ
14.7kΩ
13.3 kΩ
10.5 kΩ
8.87 kΩ
6.98 kΩ
6.04 kΩ
0.848V
0.880V
0.899V
0.919V
0.965V
43.2 kΩ
36.5 kΩ
33.2 kΩ
30.1 kΩ
25.5 kΩ
2.295V
2.506V
3.30V
5.00V
4.32 kΩ
3.74 kΩ
2.61 kΩ
1.50 kΩ
UVLO (POLA Mode)
In POLA mode 1 and 2, undervoltage threshold
(UVLO) is set following POLA standard methodol-
ogy.
In the POLA standard, a resistor on the UVLO pin sets
the corresponding voltage value.
For a module supplier, a 1.5 kΩ 1% pull-up resistor
from EN to UVLO is required to be compatible with
the POLA Inhibit/UVLO features (Figure 12). EN
must be driven by an open collector/drain driver, and
will default to Enabled unless pulled low. The driver
must remain open after a transition for a minimum of 1
ms to allow the measurement of the resistor on the
UVLO pin.
By default UVLO is set to 4.5V.
16 FN6849.0
February 18, 2009










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