DataSheet8.cn


PDF ( 数据手册 , 数据表 ) ADRF6655

零件编号 ADRF6655
描述 Broadband Up/Downconverting Mixer
制造商 Analog Devices
LOGO Analog Devices LOGO 


1 Page

No Preview Available !

ADRF6655 数据手册, 描述, 功能
Broadband Up/Downconvertwinwwg.DaMtaSihxeeet4rU.cwomith
Integrated Fractional-N PLL and VCO
ADRF6655
FEATURES
Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
Input P1dB: 12 dBm
Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP
GENERAL DESCRIPTION
The ADRF6655 is a high dynamic range active mixer with
integrated PLL and VCO. The synthesizer uses a programmable
integer-N/fractional-N PLL to generate a local oscillator input
to the mixer. The PLL reference input is nominally 20 MHz. The
reference input can be divided by or multiplied by and then
applied to the PLL phase detector. The PLL can support input
reference frequencies from 10 MHz to 160 MHz. The phase
detector output controls a charge pump whose output is integrated
in an off-chip loop filter. The loop filter output is then applied to an
integrated VCO. The VCO output at 2 × fLO is then applied to a local
oscillator (LO) divider as well as to a programmable PLL divider.
The programmable divider is controlled by an Σ-Δ modulator
(SDM). The modulus of the SDM can be programmed between
1 and 2047.
The broadband, active mixer employs a bias adjustment to allow
for enhanced IP3 performance at the expense of increased supply
current. The mixer provides an input IP3 exceeding 25 dBm
with 12 dB single sideband NF under typical conditions. The IIP3
can be boosted to ~29 dBm with roughly 20 mA of additional
supplied current. The mixer provides a typical voltage conversion
gain of 6 dB with a 200 Ω differential IF output impedance. The
IF output can be externally matched to support upconversion over
a limited frequency range.
The ADRF6655 is fabricated using an advanced silicon-germanium
BiCMOS process. It is packaged in a 40-lead, exposed-paddle,
Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a
−40°C to +85°C temperature range.
LON 37
LOP 38
GND 11
DATA 12
CLK 13
LE 14
GND 15
REFIN 6
GND 7
MUXOUT 8
GND GND VCCLO
36 35
34
FUNCTIONAL BLOCK DIAGRAM
LOSEL
BUFFER
NC NC GND
33 32 31
ADRF6655
30 GND
29 IP3SET
28 GND
27 VCCMIX
SPI
INTERFACE
×2
MUX
÷2
÷4
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
21 TO 123
BUFFER
LOSEL
PRESCALER
MUX
DIVIDER
÷2 OR ÷3
VCO
CORE
TEMP
SENSOR
+
PHASE
FREQUENCY
DETECTOR
3.3V LDO
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
2.5V LDO
VCO LDO
26 INP
25 INN
24 GND
23 GND
22 VCCV2I
21 GND
1
VCC1
2
DECL1
34
5
9 10 39 40 16 17 18 19 20
CP GND RSET DECL2 VCC2 VTUNE DECL3 NC VCCLO OUTN OUTP GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.







ADRF6655 pdf, 数据表
ADRF6655
Pin No.
5
Mnemonic
RSET
6 REFIN
8 MUXOUT
9
10
12
13
14
16, 32, 33
17, 34
18,19
22
25, 26
27
29
37, 38
DECL2
VCC2
DATA
CLK
LE
NC
VCCLO
OUTN, OUTP
VCCV2I
INN, INP
VCCMIX
IP3SET
LON, LOP
39 VTUNE
40 DECL3
EPAD (EP)
www.DataSheet4U.com
Description
Charge Pump Current. The nominal charge pump current can be set to either 250 μA, 500 μA, 750 μA,
or 1 mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current).
In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents
(INOMINAL) can be externally tweaked according to
RSET
[Ω ] =
217 .4 × I CP ,BASE
⎢⎣ 250
⎥⎦
37 .8
where ICP, BASE is the base charge pump current in μA.
For further details on the charge pump current,see the Register 4—Charge Pump, PFD, and Reference
Path Control section.
Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz. This pin must be
ac-coupled.
Multiplexer Output. This output allows either a digital lock detect, a voltage proportional to temperature,
or a buffered, frequency-scaled reference signal to be accessed externally. The output is selected by
programming the appropriate bits in Register 4.
Decoupling Node for 2.5 V LDO. Pin should be decoupled with 100 pF, 0.1 μF, and 10 μF capacitors
located close to the pin.
Power Supply for Internal 2.5 V LDO. The power supply voltage range is 4.75 V to 5.25 V. Supply pin
should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.
Serial Data Input. The serial data input is loaded MSB first with the three LSBs being the control bits.
Serial Clock Input. This serial clock input is used to clock in the serial data to the registers. The data
is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one
of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.
No Connection.
Power Supply for LO Path. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be
decoupled with 100 pF and 0.1 μF capacitors located close to the pin.
Mixer IF Outputs. These pins should be pulled to VCC with RF chokes.
Power Supply for Voltage to Current Input Stage. The power supply voltage range is 4.75 V to 5.25 V.
Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.
Mixer RF Inputs. Differential RF Inputs. Internally matched to 50 Ω. This pin must be ac-coupled.
Power Supply for Mixer. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be
decoupled with 100 pF and 0.1 μF capacitors located close to the pin.
Connect Resistor to VCC to Adjust IP3.
Local Oscillator Input/Output. The internally generated 1 × fLO is available on these pins. When internal
LO generation is disabled, an external 2 × fLO or 3 × fLO (depending on divider selection) can be applied
to these pins. This pin must be ac-coupled.
VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage
range on this pin is 1 V to 2.8 V.
Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin
and ground.
The exposed paddle should be soldered to a low impedance ground plane.
Rev. 0 | Page 8 of 44







ADRF6655 equivalent, schematic
ADRF6655
www.DataSheet4U.com
COMPLIMENTARY CUMULATIVE DISTRIBUTION FUNCTION (CCDF): UPCONVERSION DISTRIBUTION
100
95
90
85
80
75 GAIN
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–10 –8 –6 –4 –2
0
IP3SET = 3.2V
IP3SET = OPEN
OUTPUT P1dB
+25°C
–40°C
+85°C
2 4 6 8 10 12 14 16 18 20
100
+25°C
90 –40°C
+85°C
80
70
60
50
GAIN
OUTPUT P1dB
40
30
20
10
IP3SET = 3.2V
IP3SET = OPEN
0
–10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20
GAIN (dB), OUTPUT P1dB (dBm)
GAIN (dB), OUTPUT P1dB (dBm)
Figure 43. Gain and Output P1dB CCDF, LO = 1220 MHz, RF = 340 MHz
Figure 46. Gain and Output P1dB CCDF, LO = 1840 MHz, RF = 340 MHz
100
IP3SET = 3.2V
90 IP3SET = OPEN
80
+25°C
–40°C
+85°C
70
60
50
40
30
20
10
0
0 5 10 15 20 25 30 35 40 45 50 55 60
OUTPUT IP3 (dBm)
Figure 44. Output IP3 CCDF, LO = 1220 MHz, RF = 340 MHz
100
IP3SET = 3.2V
90 IP3SET = OPEN
80
+25°C
–40°C
+85°C
70
60
50
40
30
20
10
0
0 5 10 15 20 25 30 35 40 45 50 55 60
OUTPUT IP3 (dBm)
Figure 47. Output IP3 CCDF, LO = 1840 MHz, RF = 340 MHz
100
95 IP3SET = 3.2V
90 IP3SET = OPEN
+25°C
–40°C
85 +85°C
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
LO-TO-IF OUTPUT LEAKAGE (dBm)
Figure 45. LO-to-IF Output Leakage CCDF, LO = 1220 MHz, RF = 340 MHz
100
95 IP3SET = 3.2V
+25°C
90 IP3SET = OPEN
–40°C
85 +85°C
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
LO-TO-IF PORT LEAKAGE (dBm)
Figure 48. LO-to-IF Output Leakage CCDF, LO = 1840 MHz, RF = 340 MHz
Rev. 0 | Page 16 of 44










页数 30 页
下载[ ADRF6655.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
ADRF6655Broadband Up/Downconverting MixerAnalog Devices
Analog Devices
ADRF6658Dual Rx MixersAnalog Devices
Analog Devices

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap