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PDF ( 数据手册 , 数据表 ) CY14B101Q3

零件编号 CY14B101Q3
描述 1 Mbit (128K x 8) Serial SPI nvSRAM
制造商 Cypress Semiconductor
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CY14B101Q3 数据手册, 描述, 功能
CY14B101Q1
CY14B101Q2
www.DataSheet4U.com
CY14B101Q3
1 Mbit (128K x 8) Serial SPI nvSRAM
Features
1 Mbit Nonvolatile SRAM
Internally organized as 128K x 8
STORE to QuantumTrap Nonvolatile Elements initiated au-
tomatically on Power Down (AutoStore) or by user using HSB
Pin (Hardware Store) or SPI instruction (Software Store)
RECALL to SRAM initiated on Power Up (Power Up Recall)
or by SPI Instruction (Software RECALL)
Automatic STORE on Power Down with a small Capacitor
High Reliability
Infinite Read, Write, and RECALL Cycles
1 Million STORE cycles to QuantumTrap
Data Retention: 20 Years
High Speed Serial Peripheral Interface (SPI)
40 MHz Clock Rate
Supports SPI Modes 0 (0,0) and 3 (1,1)
Write Protection
Hardware Protection using Write Protect (WP) Pin
Software Protection using Write Disable Instruction
Software Block Protection for 1/4,1/2, or entire Array
Low Power Consumption
Single 3V +20%, –10% Operation
Average VCC current of 10 mA at 40 MHz Operation
Industry Standard Configurations
Industrial Temperature
CY14B101Q1 has identical pin configuration to industry stan-
dard 8-pin NV Memory
8-pin DFN and 16-pin SOIC Packages
RoHS Compliant
Logic Block Diagram
Functional Overview
The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3
combines a 1 Mbit nonvolatile static RAM with a nonvolatile
element in each memory cell. The memory is organized as 128K
words of 8 bits each. The embedded nonvolatile elements incor-
porate the QuantumTrap technology, creating the world’s most
reliable nonvolatile memory. The SRAM provides infinite read
and write cycles, while the QuantumTrap cell provides highly
reliable nonvolatile storage of data. Data transfers from SRAM to
the nonvolatile elements (STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
Both STORE and RECALL operations can also be triggered by
the user.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B101Q1
No
Yes
CY14B101Q2
Yes
Yes
CY14B101Q3
Yes
Yes
No No Yes
VCC
VCAP
CS
WP
SCK
HOLD
SI
Instruction decode
Write protect
Control logic
Quantum Trap
128K X 8
SRAM ARRAY
128K X 8
STORE
RECALL
Instruction
register
Address
Decoder
A0-A16
D0-D7
Data I/O register
Power Control
STORE/RECALL
Control
HSB
SO
Status register
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-50091 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 04, 2010







CY14B101Q3 pdf, 数据表
CY14B101Q1
CY14B101Q2
wwCw.YDa1ta4ShBee1t40U1.cQom3
SPI Operating Features
Power Up
Power up is defined as the condition when the power supply is
turned on and VCC crosses Vswitch voltage. During this time, the
Chip Select (CS) must be allowed to follow the VCC voltage.
Therefore, CS must be connected to VCC through a suitable pull
up resistor. As a built-in safety feature, Chip Select (CS) is both
edge sensitive and level sensitive. After power up, the device is
not selected until a falling edge is detected on Chip Select (CS).
This ensures that Chip Select (CS) must have been HIGH,
before going Low to start the first operation.
As described earlier, nvSRAM performs a Power Up Recall
operation after power up and therefore, all memory accesses are
disabled for tRECALL duration after power up. The HSB pin can
be probed to check the ready or busy status of nvSRAM after
power up.
Power On Reset
A Power On Reset (POR) circuit is included to prevent
inadvertent writes. At power up, the device does not respond to
any instruction until the VCC reaches the Power On Reset
threshold voltage (VSWITCH). After VCC transitions the POR
threshold, the device is internally reset and performs an Power
Up Recall operation. The device is in the following state after
POR:
Deselected (after Power up, a falling edge is required on Chip
Select (CS) before any instructions are started).
Standby power mode
Not in the hold condition
Status register state:
Write Enable (WEN) bit is reset to 0.
WPEN, BP1, BP0 unchanged from previous power down
The WPEN, BP1, and BP0 bits of the Status Register are nonvol-
atile bits and remain unchanged from the previous power down.
Before selecting and issuing instructions to the memory, a valid
and stable VCC voltage must be applied. This voltage must
remain valid until the end of the transmission of the instruction.
Power Down
At power down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress during power down, it is allowed
tDELAY time to complete after Vcc transitions below VSWITCH,
after which all memory accesses are inhibited and a conditional
AutoStore operation is performed (AutoStore is not performed if
no writes have happened since last RECALL cycle). This feature
prevents inadvertent writes to nvSRAM from happening during
power down.
However, to completely avoid the possibility of inadvertent writes
during power down, ensure that the device is deselected and is
in Standby Power Mode, and the Chip Select (CS) follows the
voltage applied on VCC.
Active Power and Standby Power Modes
When Chip Select (CS) is LOW, the device is selected, and is in
the Active Power mode. The device consumes ICC current, as
specified in DC Electrical Characteristics on page 14. When Chip
Select (CS) is HIGH, the device is deselected and the device
goes into the Standby Power mode if a STORE or RECALL cycle
is not in progress. If a STORE or RECALL cycle is in progress,
device goes into the Standby Power Mode after the STORE or
RECALL cycle is completed. In the Standby Power mode, the
current drawn by the device drops to ISB.
SPI Functional Description
The CY14B101Q1/CY14B101Q2/CY14B101Q3 uses an 8-bit
instruction register. Instructions and their opcodes are listed in
Table 3. All instructions, addresses, and data are transferred with
the MSB first and start with a HIGH to LOW CS transition. There
are, in all, 12 SPI instructions which provide access to most of
the functions in nvSRAM. Further, the WP and HOLD pins
provide additional functionality driven through hardware.
Table 3. Instruction Set
Instruction
Category
Instruction
Name
Opcode
Operation
WREN
0000 0110 Set Write Enable
Latch
Status Register
Control Instruc-
tions
WRDI
RDSR
0000 0100
0000 0101
Reset Write
Enable Latch
Read Status
Register
WRSR
0000 0001
Write Status
Register
SRAM
Read/Write
Instructions
READ
WRITE
0000 0011
0000 0010
Read Data From
Memory Array
Write Data To
Memory Array
STORE 0011 1100 Software STORE
Special NV
Instructions
RECALL
ASENB
0110 0000
Software
RECALL
0101 1001 AutoStore Enable
ASDISB 0001 1001
AutoStore
Disable
Reserved
- Reserved - 0001 1110
Reserved for
Internal use
The SPI instructions are divided based on their functionality in
the following types:
Status Register Access: WRSR and RDSR instructions
Write Protection Functions: WREN and WRDI instructions
along with WP pin and WEN, BP0, and BP1 bits
SRAM memory Access: READ and WRITE instructions
nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
Document #: 001-50091 Rev. *D
Page 8 of 24







CY14B101Q3 equivalent, schematic
CY14B101Q1
CY14B101Q2
wwCw.YDa1ta4ShBee1t40U1.cQom3
AC Switching Characteristics
Cypress
Parameter
fSCK
tCL
tCH
tCS
tCSS
tCSH
tSD
tHD
tHH
tSH
tCO
tHHZ
tHLZ
tOH
tHZCS
fSCK
tWL
tWH
tCE
tCES
tCEH
tSU
tH
tHD
tCD
tV
tHZ
tLZ
tHO
tDIS
Alt.
Parameter
Description
Clock Frequency, SCK
Clock Pulse Width Low
Clock Pulse Width High
CS High Time
CS Setup Time
CS Hold Time
Data In Setup Time
Data In Hold Time
HOLD Hold Time
HOLD Setup Time
Output Valid
HOLD to Output High Z
HOLD to Output Low Z
Output Hold Time
Output Disable Time
Figure 21. Synchronous Data Timing (Mode 0)
CS
SCK
SI
SO HI-Z
CS
tCSS
tCH
tSD tHD
VALID IN
tCL
tCO
Figure 22. HOLD Timing
40MHz
Min Max
40
11
11
20
10
10
5
5
5
5
9
15
15
0
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCSH
tCS
tOH tHZCS
HI-Z
SCK
HOLD
SO
Document #: 001-50091 Rev. *D
tHH
tSH
tHHZ
tHH
tSH
tHLZ
Page 16 of 24










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