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PDF ( 数据手册 , 数据表 ) LC72191M

零件编号 LC72191M
描述 PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners
制造商 Sanyo Semicon Device
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LC72191M 数据手册, 描述, 功能
Ordering number : EN 3985C
CMOS LSI
LC72191, 72191M, 72191JM
PLL Frequency Synthesizer
for Electronic Tuning in Car Stereo Tuners
Overview
The LC72191, LC72191M and LC72191JM are PLL
frequency synthesizers for electronic tuning. The
LC72191, LC72191M and LC72191JM are optimal for
AM/FM tuner circuits that require high mounting
densities.
Features
Designed for use in car stereos, the LC72191 provides a
rich set of reference frequencies, I/O ports, a general-
purpose counter, and an unlock detection circuit.
Functions
• Programmable dividers
— FMIN pin: 130 MHz at 70 mVrms and 160 MHz at
100 mVrms input (built-in prescaler)
— AMIN pin: Pulse swallower and direct division
techniques
• Reference frequencies: Ten selectable frequencies:
1, 5, 9, 10, 3.125, 6.25, 12.5 25, 50 and 100 kHz
• Output ports: 7 pins
Complementary outputs: 2 pins
N-channel open drain outputs: 5 pins
• Input ports: 2 pins
• General-purpose counter: For measuring IF and other
signals (Also used for station detection when
functioning as an IF counter.)
— HCTR pin: Frequency measurement (for inputs up to
70 MHz)
— LCTR pin: Frequency and period measurement
• PLL unlock detection circuit
Detects phase differences of 0.55, 1.11, 2.22 and 3.33 µs.
• Controller clock output: 400 kHz
• Clock time base output: 8 Hz
• Serial data I/O
— Supports CCB format communication with the
system controller.
• Package: LC72191: DIP24S
LC72191M: MFP24
LC72191JM: MFP24S
Package Dimensions
unit: mm
3067-DIP24S
[LC72191]
SANYO: DIP24S
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D3096HA (OT)/D2593JN/6182JN No. 3985-1/16







LC72191M pdf, 数据表
LC72191, 72191M, 72191JM
No. Control block/data
Description
Related data
Programmable divider
(1) data
D0 to D15
• This data sets up the programmable divider.
D0 to D15 is a binary value with D15 as the MSB.
The position of the LSB is changed by DV and SP as listed in the table below.
DV SP LSB
Divisor setting
Actual divisor
1*
D0 256 to 65536
Twice the set value
01
D0 256 to 65536
The set value
00
D4 4 to 4096
The set value
* don’t care
When D4 is the LSB, bits D0 to D3 are ignored.
DV
SP
Output port data
(2) O0 to O6
• Data that determines the states of the output ports OUT0 to OUT6. O0 determines the
OUT0 pin output. However, note that when O0 is 0, OUT0 will output a high level, and when O0
is 1, OUT0 will output a low level. O1 to O6 function in the same manner.
• These can be used for a wide range of purposes, including, for example, band switching
signals.
• When the TB bit is set to 1, the O0 data is ignored and the OUT0 pin outputs an 8 Hz clock
time base signal.
• Since the output port states are undefined when power is first applied, transfer the control data
quickly.
TB
• Data that determines the operation of the general-purpose counter. When CTEN is 0, the 20-bit
binary counter (the general-purpose counter) is reset and the HCTR and LCTR pins are pulled
General-purpose counter down to ground. When CTEN is set to 1, the general-purpose counter reset state is cleared and
(3) initial data
the counter operates according to the SC bit (the general-purpose selection data). In this state,
CTEN
the general-purpose counter will count either the HCTR or LCTR input signal.
• Since the general-purpose counter is reset by setting CTEN to 0, the result of a count operation
must be sent to the controller while CTEN is still 1.
SC
SF
GT
Reference frequency
(4) data
R0 to R3
• Data that selects one of the ten LC72191 reference frequencies or sets the LC72191 to
backup mode in which PLL operation is disabled.
R0 R1 R2 R3
00 00
Reference frequency (kHz)
100
00 01
50
00 10
25
00 11
25
01 00
12.5
01 01
6.25
01 10
3.125
01 11
3.125
10 00
10
10 01
9
10 10
5
10 11
1
11 00
11 01
PLL inhibit state*
11 10
11 11
Note: * PLL inhibit (backup mode)
The programmable divider block is turned off, both the FMIN and AMIN pins are pulled
down to ground, and the charge pump outputs go to the floating state.
Continued on next page.
No. 3985-8/16







LC72191M equivalent, schematic
LC72191, 72191M, 72191JM
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s Anyone purchasing any products described or contained herein for an above-mentioned use shall:
ΠAccept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
No. 3985-16/16










页数 16 页
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