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PDF ( 数据手册 , 数据表 ) AD9269

零件编号 AD9269
描述 1.8 V Dual Analog-to-Digital Converter
制造商 Analog Devices
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AD9269 数据手册, 描述, 功能
Data Sheet
16-Bit, 20/40/65/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9269
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND
SDIO SCLK CSB
VIN+A
VIN–A
AD9269
SPI
ADC
PROGRAMMING DATA
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
QUADRATURE
ERROR
CORRECTION
ADC
DIVIDE DUTY CYCLE
1 TO 6 STABILIZER
MODE
CONTROLS
ORA
D15A
D0A
DCOA
DRVDD
ORB
D15B
D0B
DCOB
CLK+ CLK–
SYNC
DCS
Figure 1.
PDWN DFS OEB
PRODUCT HIGHLIGHTS
1. The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
4. A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
5. The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC
the AD9231 12-bit ADC, the AD6659 12-bit baseband
diversity receiver, and the AD9204 10-bit ADC, enabling a
simple migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







AD9269 pdf, 数据表
AD9269
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
With QEC Active
Wake-Up Time2
Standby
OUT-OF-RANGE RECOVERY TIME
AD9269-20/AD9269-40
Temp Min Typ
Max
AD9269-65
AD9269-80
Min Typ Max Min Typ Max Unit
Full 480 480 480 MHz
Full 3
20/40 3
65 3
80 MSPS
Full 50/25
15.38 12.5 ns
25.0/12.5
7.69 6.25 ns
Full 1.0
1.0 1.0 ns
Full 0.1
0.1 0.1 ps rms
Full 3
Full 3
Full 0.1
Full 9
Full 11
Full 350
Full 600/400
Full 2
3 3 ns
3 3 ns
0.1 0.1 ns
9 9 Cycles
11 11 Cycles
350 350 μs
300 260 ns
2 2 Cycles
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
N–1
tA
N
VIN
N+3
N+4
N+5
N+1
N+2
CLK+
CLK–
DCOA/DCOB
tCH tCLK
tDCO
tSKEW
CH A/CH B DATA
N–9
N–8
N–7
N–6
N–5
tPD
Figure 2. CMOS Output Data Timing
N–1
tA
N
VIN
N+3
N+4
N+5
N+1
N+2
CLK+
tCH tCLK
CLK–
DCOA/DCOB
tDCO
CH A/CH B DATA
AS APPEARS ON
CHA OUTPUT PINS
tSKEW
CH A CH B
N–9 N–9
tPD
CH A
N–8
CH B
N–8
CH A
N–7
CH B
N–7
CH A
N–6
CH B
N–6
Figure 3. CMOS Interleaved Output Timing, Output as Appears on Channel A Output Pins
CH A
N–5
Rev. A | Page 8 of 40







AD9269 equivalent, schematic
AD9269
Data Sheet
AD9269-40
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
0
40MSPS
9.7MHz @ –1dBFS
–20 SNR = 76.9dB (77.9dBFS)
SFDR = 95.1dBc
–40
–60
–80
–100
120
SFDRFS
100
80
SNRFS
SFDR
60
40
SNR
–120
20
–140
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 23. AD9269-40 Single-Tone FFT with fIN = 9.7 MHz
0
–65 –60
–50 –40 –30 –20
INPUT AMPLITUDE (dBFS)
–10
0
Figure 25. AD9269-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
0
40MSPS
30.6MHz @ –1dBFS
–20 SNR = 76.6dB (77.6dBFS)
SFDR = 88.8dBc
–40
–60
–80
–100
–120
–140
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 24. AD9269-40 Single-Tone FFT with fIN = 30.6 MHz
Rev. A | Page 16 of 40










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