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PDF ( 数据手册 , 数据表 ) D75006

零件编号 D75006
描述 UPD75006
制造商 NEC
LOGO NEC LOGO 


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D75006 数据手册, 描述, 功能
DATA SHEET
MOS INTEGRATED CIRCUIT
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µPD75004, 75006, 75008
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75008 is one of the 75X Series 4-bit single-chip microcomputer.
In addition to high-speed operation with 0.95 µs minimum instruction execution time for the CPU, the
µPD75008 employs a serial bus interface with standard NEC format, the µPD75004 is a powerful product with
a high cost/performance ratio.
The µPD75P008 with PROM, which is provided with µPD75008, is applicable for evaluating systems under
development, or for small-scale production of developed systems.
Detailed functions are described in the following user’s manual. Be sure to read it for designing.
µPD7500X Series User’s Manual: IEM-5033
FEATURES
Capable of high-speed operation and variable instruction execution time to power save
• 0.95 µs, 1.91 µs, 15.3 µs (Main system clock: operating at 4.19 MHz)
• 122 µs (Subsystem clock: operating at 32.768 kHz)
75X architecture comparable to that for an 8-bit microcomputer is employed
Built-in NEC standard serial bus interface (SBI)
Clock operation at reduced power dissipation (5 µA TYP. : operating at 3 V)
Enhanced timer function (3 channels)
Interrupt functions especially enhanced for applications, such as remote control receiver
APPLICATIONS
VCRs, CD players, telephones, cameras, blood pressure gauges, etc.
Unless otherwise specified, µPD75008 is treated as the representative model throughout this manual.
The information in this document is subject to change without notice.
Document No. IC-2633C
(O. D. No. IC-7673E)
Date Published November 1993 P
Printed in Japan
The mark 5 shows major revised points.
© NEC Corporation 1990







D75006 pdf, 数据表
TI0/P13
PTO0/P20
BUZ/P23
BASIC
INTERVAL
TIMER
INTBT
TIMER/EVENT
COUNTER
#0
INTT0
WATCH
TIMER
INTW
SI/SB1/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60
–KR7/P73
CLOCKED
SERIAL
INTERFACE
INTCSI
INTERRUPT
CONTROL
BIT SEQ.
BUFFER (16)
PROGRAM
COUNTER *
PROGRAM
MEMORY
(ROM)
4096 × 8 BITS
(µPD75004)
6016 × 8 BITS
(µPD75006)
8064 × 8 BITS
(µPD75008)
SP (8)
CY
ALU
BANK
DECODE
AND
CONTROL
GENERAL REG.
DATA
MEMORY
(RAM)
512 × 4 BITS
CLOCK
OUTPUT
CONTROL
fX /2 N
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR
SUB MAIN
STAND BY
CONTROL
CPU
CLOCK
PCL/P22
XT1 XT2 X1 X2
V DD V SS RESET
*: For µPD75004, 12 bits. For µPD75006 and µPD75008, 13 bits.
PORT 0 4 P00-P03
PORT 1 4 P10-P13
PORT 2 4 P20-P23
PORT 3 4 P30-P33
PORT 4 4 P40-P43
PORT 5 4 P50-P53
PORT 6 4 P60-P63
PORT 7 4 P70-P73
PORT 8 2 P80-P81







D75006 equivalent, schematic
µPD75004, 75006, 75008
4. MEMORY CONFIGURATION
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Program memory (ROM) ... 4096 × 8 bits (0000H-0FFFH) : µPD75004
... 6016 × 8 bits (0000H-177FH) : µPD75006
... 8064 × 8 bits (0000H-1F7FH) : µPD75008
• 0000H-0001H : Vector table to which address from which program is started is written after reset
• 0002H-000BH: Vector table to which address from which program is started is written after interrupt
• 0020H-007FH : Table area referenced by GETI instruction
Data memory (RAM)
• Data area .... 512 × 4 bits (000H–1FFH)
• Peripheral hardware area .... 128 × 4 bits (F80H–FFFH)
Address
7654
000H MBE 0 0 0 Internal reset start address (upper 4 bits)
Internal reset start address (lower 8 bits)
002H MBE 0 0 0 INTBT/INT4 start address (upper 4 bits)
INTBT/INT4 start address (lower 8 bits)
004H MBE 0 0 0 INT0 start address (upper 4 bits)
INT0 start address (lower 8 bits)
006H MBE 0 0 0 INT1 start address (upper 4 bits)
INT1 start address (lower 8 bits)
008H MBE 0 0 0 INTCSI start address (upper 4 bits)
INTCSI start address (lower 8 bits)
00AH MBE 0 0 0 INTT0 start address (upper 4 bits)
INTT0 start address (lower 8 bits)
0
CALLF
!faddr
instruction
entry
address
CALL ! addr
instruction
subroutine
entry address
BRCD ! caddr
instruction
branch address
020H
07FH
080H
GETI instruction reference table
BR $addr
instruction
relational
branch address
(–15 to –1,
+2 to +16)
7FFH
800H
Branch destination
address and
subroutine entry
address for
GETI instruction
FFFH
16
Fig. 4-1 Program Memory Map (µPD75004)










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