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PDF ( 数据手册 , 数据表 ) ORSO82G5

零件编号 ORSO82G5
描述 (ORSO42G5 / ORSO82G5) 0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
制造商 Lattice Semiconductor
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ORSO82G5 数据手册, 描述, 功能
ORCA® ORSO42G5 and ORSO82G5www.DataSheet4U.com
0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
July 2008
Data Sheet DS1028
Introduction
Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5
devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSO42G5 and
ORSO82G5 are high-speed transceivers with aggregate bandwidths of over 10 Gbps and 20 Gbps respectively.
These devices are targeted toward users needing high-speed backplane interfaces for SONET and other non-
SONET applications. The ORSO42G5 has four channels and the ORSO82G5 has eight channels of integrated 0.6-
2.7Gbps SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable
FPGA system gates. The CDR circuitry, available from Lattice’s high-speed I/O portfolio (sysHSI™), has already
been used in numerous applications to create STS-48/STM-16 and STS-192/STM-64 SONET/SDH interfaces.
With the addition of protocol and access logic, such as framers and Packet-over-SONET (PoS) interfaces, design-
ers can build a configurable interface using proven backplane driver/receiver technology. Designers can also use
the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. The
ORSO42G5 and ORSO82G5 can also be used to provide a full 10 Gbps backplane data connection and, with the
ORSO82G5, support both work and protection connections between a line card and switch fabric.
The ORSO42G5 and ORSO82G5 support a clockless high-speed interface for interdevice communication on a
board or across a backplane. The built-in clock recovery of the ORSO42G5 and ORSO82G5 allows higher system
performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network
designers will benefit from using the backplane transceiver as a network termination device. Sister devices, the
ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet
(XAUI) and Fibre Channel. The ORSO42G5 and ORSO82G5 perform SONET data scrambling/descrambling,
streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to termi-
nate the network into proprietary systems. The cell processing feature in the ORSO42G5 and ORSO82G5 makes
them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET
applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The
ORSO42G5 and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.
Table 1. ORCA ORSO42G5 and ORSO82G5 Family – Available FPGA Logic
Device
PFU
FPGA Max
PFU Rows Columns Total PFUs User I/O
LUTs
EBR
Blocks2
EBR Bits
(K)
FPGA
System
Gates (K)1
ORSO42G5
36
36
1296
204 10,368 12
111 333-643
ORSO82G5
36
36
1296
372 10,368 12
111 333-643
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate
ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with
40% EBR usage and 2 PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80%
EBR usage and 4 PLLs.
2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.
.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1028_08.0







ORSO82G5 pdf, 数据表
Lattice Semiconductor
ORCA ORSO42G5 and ORSOw8w2wG.D5atDaSahteaetS4Uh.ceoemt
device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplex-
ing, uplink and downlink functions, and other functions on two output signals. Large blocks of 512 x 18 block-port
RAM complement the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM,
FIFO, multiplier, and CAM. Some of the other system-level functions include the MPI, PLLs, and the Embedded
System Bus (ESB).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional Flip-Flop that
may be used independently or with arithmetic functions.
The PFU is organized in a twin-block fashion; two sets of four LUTs and FFs that can be controlled independently.
Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may
also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The
carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a
synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or
directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock
polarity, clock enables, and local set/reset.
The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidi-
rectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional
INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU
outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for real-
world system performance.
Programmable I/O
The Series 4 PIO addresses the demand for the flexibility to select I/Os that meet system interface requirements.
I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features which
allow the user the flexibility to select new I/O types that support High-Speed Interfaces.
Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA
array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset,
and global set/reset. On the input side, each PIO contains a programmable latch/Flip-Flop which enables very fast
latching of data from any pad. The combination provides for very low setup requirements and zero hold times for
signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data sig-
nal, and register the signals without explicitly building a demultiplexer with a PFU.
On the output side of each PIO, an output from the PLC array can be routed to each output Flip-Flop, and logic can
be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals
and other functions of two output signals.
The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to
be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal
can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-
state signal can be registered or nonregistered.
The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These
modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing
data rates. This new logic block also supports high-speed DDR mode requirements where data are clocked into
and out of the I/O buffers on both edges of the clock.
The new programmable I/O cell allows designers to select I/Os which meet many new communication standards
permitting the device to hook up directly without any external interface translation. They support traditional FPGA
standards as well as high-speed, single-ended, and differential-pair signaling. Based on a programmable, bank-ori-
ented I/O ring architecture, designs can be implemented using 3.3V, 2.5V, 1.8V, and 1.5V referenced output levels.
8







ORSO82G5 equivalent, schematic
Lattice Semiconductor
ORCA ORSO42G5 and ORSOw8w2wG.D5atDaSahteaetS4Uh.ceoemt
ORSO42G5 and ORSO82G5 Embedded Core Detailed Description
The ORSO42G5 and ORSO82G5 have four and eight channels respectively, with a high-speed SERDES macro
that performs clock data recovery, serializing and deserializing functions. There is also additional logic for SONET
mode and cell mode data synchronization formatting and scrambling/descrambling. For all modes, the data paths
can be characterized as the transmit path (FPGA to backplane) and receive path (backplane to FPGA); however
the interface signal assignments between the FPGA logic and the core differ depending on the operating mode
selected.
The three main operating modes in the ORSO42G5 and ORSO82G5 are:
• SERDES only mode
• SONET mode
• Cell mode
– Two-link sub-mode
– Eight-link sub-mode (ORSO82G5 only)
The SONET and cell modes each support sub-modes that can be selected by enabling or disabling certain func-
tions through programmable register bits. Following the basic TX and RX architecture descriptions, the data format-
ting and logical implementations supporting each of the operational modes are described.
Top Level Description - Transmitter (TX) and Receiver (RX) Architectures
The next sections give a top level description of the transmitter and receive architectures. The high-speed transmit
and receive serial data can operate at 0.6-2.7 Gbps depending on the state of the control bits from the system bus
and the provided reference clock. For all of the architecture and clock distribution descriptions, however, the stan-
dard SONET STS-48 rate of 2,488.32 Mbits/s (i.e., REFCLK_[P:N] = 155.52 MHz for the full rate modes) is
assumed.
Transmitter Architecture
The transmitter section accepts parallel data for transmission from the FPGA logic, formats it for transmission and
serializes the data. It also accepts the low-speed reference clock at the REFCLK input and uses this clock to syn-
thesize the internal high-speed serial bit clock. The serialized transmitted data are available at the differential CML
output pins to drive either an optical transmitters, coaxial media or a circuit board backplane.
The top level transmit architecture is shown in Figure 3. The main logical blocks in the transmit path are:
• Output Port Controllers (OPCs) which contain the cell processing logic.
• SONET processing logic.
• Transmit SERDES and 32:8 MUX.
Depending on the mode of operation, the FPGA to backplane data path may include or bypass the various logical
blocks.
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